Liebe Studierende,

wir bemühen uns, das Lehrangebot des Lehrstuhls für Entwurfsautomatisierung für das Sommersemester 2020 trotz der aktuellen Einschränkungen weitgehend aufrecht zu erhalten. Nach momentaner Planung gehen wir davon aus, mit einer Ausnahme alle Lehrveranstaltungen anbieten zu können, ob nun Präsenz an der TUM möglich sein wird oder nicht. Sofern Präsenz nicht möglich ist, werden die Lehrveranstaltungen natürlich anders durchgeführt werden als üblicherweise, inhaltlich bedeutet dies jedoch keine Einschränkungen.

Die oben erwähnte Ausnahme ist das „VLSI Design Lab“ – dieses Praktikum können wir nur anbieten, sofern Präsenz an der TUM möglich ist. Sollte Präsenz zu Vorlesungsbeginn am 20.04.2020 nicht möglich sein, im Verlaufe der Vorlesungszeit aber wieder möglich werden, werden wir uns dann darum bemühen, dieses Praktikum noch anbieten zu können. Aber wir können dies aktuell nicht garantieren.

Bitte informieren Sie sich auch regelmäßig unter sowie ggf. die Website der Fakultät über aktuelle Informationen zur Lehre.


Bleiben Sie gesund!


Ihr Team des Lehrstuhls für Entwurfsautomatisierung der TUM.

Testing Digital Circuits

Vortragende/r (Mitwirkende/r)
Umfang3 SWS
SemesterWintersemester 2019/20
Stellung in StudienplänenSiehe TUMonline




At the end of the module students know about the following topics and are able to employ this knowledge to define and evaluate test solutions for digital ICs and systems: - Definition of testing and the difference to verification - Fundamentals of testing: fault models, fault detection, redundant faults, fault coverage - Methods for test generation: Boolean differences, D-algorithm, fault simulation - Analysis of test complexity with the help of complexity theory - Principles of passive test methods: Ad-hoc measures, scan path / Principles of active test methods: BIST - Overview over memory fault models and memory test algorithms. - Outline of test standards (IEEE boundary scan test) and additional topics like IDDQ testing, analog testing, fault analysis.


Principles of testing digital circuits; fault models and test quality; functional and structural test generation; fault simulation; complexity theory; design for test (passive, active test methods); memory test; test standards; miscellaneous topics (Iddq test, analog test, test pattern compression, yield management); In detail: The manufacturing process of integrated circuits introduces a large variety of physical defects. In order to prevent the delivery of failing silicon devices to the customer, the correct function of delivered integrated circuits has to be guaranteed by testing all devices after they have been fabricated. Testing integrated circuits is one of the core competencies of a semiconductor company. It represents a significant factor in costs and quality. Therefore, testing is considered as an outstanding part of the entire design and manufacturing process of ICs. Furthermore, testing is a domain-crossing topic: The test engineer within a semiconductor company requires a broad expertise covering circuit and system design, circuit simulation and design verification, and physical design. One of the main challenges in testing is costs which have drastically increased over the past years. The access to circuit internal transistors and nodes has to be accomplished by a limited number of external pins. This is increasingly difficult due to the continuous shrinking of device structures. This lecture conveys: * The basic idea of testing. * Relevant failure mechanisms of integrated circuits and the common fault models. * The complexity problem of testing and its resulting limitations. * Methods for test pattern generation (e.g. fault simulation and automatic test generation). * Fundamental measures for designing integrated circuits in order to raise their testability (Design-for-Testability). * Techniques for insertion of built-in self-test (BIST) in integrated circuits. * Techniques for memory testing.

Inhaltliche Voraussetzungen

Basics of digital circuit design. The following modules should be passed before taking the course: - Digital IC-Design - Electronic Design Automation

Lehr- und Lernmethoden

Learning method: In addition to the individual methods of the students consolidated knowledge is aspired by repeated lessons in exercises and tutorials. Teaching method: During the lectures students are instructed in a teacher-centered style. The exercises are held in a student-centered way. Where applicable, each of the 10 chapters of the lectures is immediately followed by an associated exercise/tutorial block.

Studien-, Prüfungsleistung

The examination will be in an oral, highly interactive and dynamic form. The student will show his/her ability to understand, apply, develop and evaluate test solutions for digital integrated circuits and systems, at the concrete example of a small digital circuit with single stuck-at faults. In detail, he/she will compute test patterns and develop parts of a scan path and of a built-in self-test. While doing so, the student will present his/her understanding of the underlying algorithms and methods, as there are e.g. D-algorithm, test complexity analysis, IEEE 1149.1 boundary scan testing, memory testing, IDDQ testing.

Empfohlene Literatur

The following literature is recommended: * Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits; M. Bushnell, V. Agrawal; Kluwer Academic Publishers, 2000. * Digital Systems Testing and Testable Design; M. Abramovici, M. Breuer, A. Friedmann; Computer Science Press, 1990