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Technische Universität München
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VHDL System Design Laboratory (Praktikum Systementwurf mit VHDL)

Vortragende/r (Mitwirkende/r)
Nummer0000001853
ArtPraktikum
Umfang4 SWS
SemesterWintersemester 2020/21
UnterrichtsspracheEnglisch
Stellung in StudienplänenSiehe TUMonline

Termine

Teilnahmekriterien

Siehe TUMonline

Lernziele

At the end of the module students will be able to analyze and evaluate System-on-Chip and embedded system concepts. They are capable of designing and creating SoCs and embedded systems with their complex system components.

Beschreibung

In WS 2020/21, the lab is planned to be done online and remote and asynchronous: Introductory videos are downloaded at any time decided by participants. Access to lab and FPGAs is half a day each week at a given time slot. Concept of System-on-Chip (SoC); build an example of an embedded system with microcontroller, bus and peripherals; first implement an encryption algorithm using a standard hardware description language; then wrap the security module as a peripheral attached to bus; design an interface between peripheral and bus; apply an FPGA design flow for embedded systems, and embedded software for testing the encryption algorithm.

Inhaltliche Voraussetzungen

Fundamentals of digital logic design; Fundamentals of programming

Lehr- und Lernmethoden

Learning method: In addition to the individual methods of the students consolidated knowledge is acquired by providing subtasks of increasing complexity and difficulty in the laboratory notes. Teaching method: Students are free to work on their own, according to their own schedule, on the laboratory tasks. Students can work on the laboratory either in institute rooms, or at home. An adviser is available who will support them in case of significant difficulties. The following kinds of media are used: * Introductory lectures * Lecture slides available * Laboratory notes with detailed descriptions of tasks and tool environments * Individual discussions with advisor

Studien-, Prüfungsleistung

Examination with the following elements: * Written examination 60 min. (40%) * project (60%) Knowledge-based teaching targets are examined with a written examination. Capabilities of designing a System on Chip are examined by a project consisting of design tasks on the System components and the system composition using a hardware description language. The examination is in form of software code and of a documentation of the design.

Empfohlene Literatur

The following literature is recommended: * ANSI, IEEE Standards Board, IEEE Standard VHDL Language Reference Manual: IEEE Std 1076-1993 , New York, 1988, ISBN 1559373768 * Peter J. Ashenden, Designer’s Guide to Vhdl, Morgan Kaufmann Publishers, 1995, ISBN 1558602704 * More literature listed in laboratory notes

Links

Zurück zur ListeNächsterVoriger

Vollständiges Lehrangebot

Bachelorbereich: BSc-EI, MSE, BSEEIT

 

WS

SS

Diskrete Mathematik für Ingenieure (BSEI, EI00460)

Discrete Mathematics for Engineers (BSEEIT) (Schlichtmann) (Januar)

 

O/P

WS

SS

Entwurf digitaler Systeme mit VHDL u. System C (BSEI, EI0690) (Ecker)

WS 20/21 block course after lecture period

O/O
 

SS

Entwurfsverfahren für integrierte Schaltungen (MSE, EI43811) (Schlichtmann)

--

WS

  

Methoden der Unternehmensführung (BSEI, EI0481) (Weigel)

--

WS

  

Praktikum System- und Schaltungstechnik (BSEI, EI0664) (Schlichtmann et al.)

--
 

SS

Schaltungssimulation (BSEI, EI06691) (Gräb/Schlichtmann)

O/O

 

Masterbereich: MSc-EI, MSCE, ICD

 

SS

Advanced Topics in Communication Electronics (MSCE, MSEI, EI79002)

?

WS

  

Aspects of Integrated Systems Technology & Design (MSCE, MSEI, EI5013) (Wurth)

--

WS

  

Electronic Design Automation (MSCE, MSEI, EI70610) (B. Li, Tseng)

--

WS

  

Design Methodology and Automation (ICD) (Schlichtmann) (Nov)

--

WS

SS

Machine Learning: Methods and Tools (MSCE, MSEI, EI71040) (Ecker)

O/O

WS

SS

SS

Mathematical Methods of Circuit Design (MSCE, MSEI, EI74042) (Gräb)

Simulation and Optimization of Analog Circuits (ICD) (Gräb) (Mai)

O/O

O/P

WS

  

Mixed Integer Programming and Graph Algorithms in Engineering Problems (MSCE, MSEI, EI71059) (Tseng)

--

WS

SS

Numerische Methoden der Elektrotechnik (MSEI, EI70440) (Schlichtmann oder Gräb)

O/P

WS

WS

SS

Seminar VLSI-Entwurfsverfahren (MSEI, EI7750) (Schlichtmann/Müller-Gritschneder)

Seminar on Topics in Electronic Design Automation (MSCE, EI77502) (Schlichtmann/Müller-Gritschneder)

O

WS

SS

Synthesis of Digital Systems (MSCE, MSEI, EI70640) (Müller-Gritschneder)

O/P

WS

  

Testing Digital Circuits (MSCE, MSEI, EI50141) (Otterstedt)

--

WS

  

Timing of Digital Circuits (MSCE, MSEI, EI70550) (B. Li, Zhang)

--

WS

SS

VHDL System Design Laboratory (MSCE, MSEI, EI7403) (Schlichtmann)

O/O

 

Die Spalte ganz rechts bezeichnet die Form der Vorlesung/Prüfung im SS 2021. O=online, P=physische Präsenz

The column on the very right denotes the type of course/exam in SS 2021. O=online, P=physical presence

 

MSE: Munich School of Engineering (TUM)

BSEEIT: Bachelor in Electrical Engineering and Information Technology (TUM-Asia)

ICD: Master of Science in Integrated Circuit Design (TUM-Asia)

MSCE: Master of Science in Communications Engineering (TUM)

MSEI: Master of Science in Elektrotechnik und Informationstechnik

BSEI: Bachelor of Science in Elektrotechnik und Informationstechnik

 

Aktuelle Infos zur Lehre/Current information on teaching: https://www.tum.de/die-tum/aktuelles/coronavirus/studium/, www.ei.tum.de

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