Foto von Pang-Yen Chou

M.Sc. Pang-Yen Chou

Technische Universität München

Lehrstuhl für Entwurfsautomatisierung (Prof. Schlichtmann)


Arcisstr. 21
80333 München


Nai-Chen Chen, Pang-Yen Chou, Helmut Graeb, Mark Po-Hung Lin
High-Density MOM Capacitor Array with Novel Mortise-Tenon Structure for Low-Power SAR ADCs
In: Design, Automation and Test in Europe (DATE)
March 2017

Pang-Yen Chou, Nai-Chen Chen, Mark Po-Hung Lin, Helmut Graeb
Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters
IEEE Transactions on Very Large Scale Integration Systems (TVLSI)

Pang-Yen Chou, Mark Po-Hung Lin, Helmut Graeb
An integrated placement and routing for ratioed capacitor array based on ILP formulation
In: VLSI Design, Automation and Test (VLSI-DAT)
April 2016

Pang-Yen Chou, Helmut Graeb
Platzierung von Kapazitäts-Arrays: ein konstruktiver Ansatz
In: edaWorkshop
May 2014