Masterarbeiten

Themen für Masterarbeiten mit einer vorgesehenen Dauer von 6 Monaten.

Angebotene Arbeiten

ThemaBetreuerGebiet
Analog Verification FlowH. GräbAnalog-EDA
Procedural Analog Module Generation with State of the Art ToolsH. GräbAnalog-EDA
Integration of feedback structure in an automatic initial sizing toolI. AbelAnalog-EDA
Internship Digital VerificationH. GräbDigitalentwurf
Advanced RISC-V ISS Coverage Metrics Solutions (at MinRES)D. Müller-G.High-Level-Modellierung
Timing Models for Ultra-fast Host-compiled Simulation of Embedded SoftwareD. Müller-G.High-Level-Modellierung
different topics on biochip testingA. Bernardini
Classification of Blood Cells using Deep Learning MethodsD. Müller-G.
Static Code Analysis Topics with C++R. Stahl
Control layer optimization for flow-based microfluidic routing fabricY. Moradi
Dynamic Droplet Barcoding Using A Fully Programmable Valve Array for Single-Cell AnalysisY. Moradi

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In Bearbeitung

ThemaBetreuerStudent
Extension of an automatic initial sizing tool for analog circuits to support three stage op ampsI. Abelreserved
Implementing the Gm/Id-Methode in an automatic sizing tool for analog circuitsI. Abelreserved
Test Generation for Digital Circuits with Wave-PipeliningB. LiAssigned
RTL Accurate Soft-Error Vulnerability Assessment for RISC-V based Pulpino-SoCU. SharifJohannes Geier, Soyed Tuhin
On-Chip Aging Sensors to Monitor NBTI Effect in Nano-Scale SRAMA. ListlShreyas Nittur Prasannakumar
Partial Reconfiguration of Runtime Monitors on FPGAsM. MettlerWaqas Ahsan
Runtime Verification of Power and Temperature RequirementsM. MettlerPatrick Dietl
Crosstalk- and Thermal-Aware Router Design for Wavelength-Routed Optical NoCsT.-M. TsengAbhinay Manandhar
Drying Time Minimization of Inkjet-Printed Design PatternsT.-M. TsengMeng Lian
Switch Design for Microfluidic Large-Scale IntegrationT.-M. TsengYanlu Ma
Control flow protection in embedded SWU. SharifAnindya Bhattacharya