Masterarbeiten

Themen für Masterarbeiten mit einer vorgesehenen Dauer von 6 Monaten.

Angebotene Arbeiten

ThemaBetreuerGebiet
Procedural Analog Module Generation with State of the Art ToolsH. GräbAnalog-EDA
Integration of feedback structure in an automatic initial sizing toolI. AbelAnalog-EDA
Countering Probing of Digital Circuits with Sensitive TimingB. LiDigitalentwurf
Internship Digital VerificationH. GräbDigitalentwurf
Advanced RISC-V ISS Coverage Metrics Solutions (at MinRES)D. Müller-G.High-Level-Modellierung
Timing Models for Ultra-fast Host-compiled Simulation of Embedded SoftwareD. Müller-G.High-Level-Modellierung
Test Coverage Solutions for Test-Driven Software DevelopmentY. MoradiHigh-Level-Modellierung
Stellenausschreibung Deutsches PatentamtH. Gräb
Using solutions of an automatic initial sizing tool to seed optimizations in WiCkeDI. Abel
Area-efficient Optical Neural NetworksLi Zhang
Control-flow extensions to RISC-V ISA for accelerated Neural Network inferenceR. Stahl
Efficient Implementation of Partial Operator Folding for Low-memory Implementation of Artificial Neural Networks on Embedded MicrocontrollersR. Stahl
RISC-V Instruction Set Extension for Activation Functions of Neural Networks R. Stahl
Static Code Analysis Topics with C++R. Stahl
Various Topics with our Open-Source Simulator ETISS (C++)R. Stahl
RTL Accurate Fault Injection for RISC-V SoCsU. Sharif
Dynamic Droplet Barcoding Using A Fully Programmable Valve Array for Single-Cell AnalysisY. Moradi
Topics on Flow-Based Microfluidic Biochips for Single-Cell Analysis (C++ or Python)Y. Moradi

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In Bearbeitung

ThemaBetreuerStudent
Extension of an automatic initial sizing tool for analog circuits to support three stage op ampsI. Abelreserved
Implementing the Gm/Id-Methode in an automatic sizing tool for analog circuitsI. Abelreserved
Entwurf und Optimierung von Rail-to-Rail OperationsverstärkernM. NeunerEileen Haardt
Test Generation for Digital Circuits with Wave-PipeliningB. LiOngoing
Development of a Virtual Prototype of a security RISC-V System on Chip D. Müller-G.Andrea Lardschneider
Automated Test Coverage Analysis for Test-Driven Software Development using ETISSY. MoradiPhilipp Fengler
TDD of Hardware-Near Software on the Instruction Set Simulator ETISSC. FoikYasal Imran
Development of a Modular Monitoring Architecture for Large-scale MPSoCsM. MettlerPhilip Grill
Partial Reconfiguration of Runtime Monitors on FPGAsM. MettlerWaqas Ahsan
Diskrete Optimierung Analoger SchaltungenM. NeunerMalek M'Hiri
Adding a Language Frontend to an ISA Code Generator ToolR. StahlNina Mutzel
Porting Neural Network Software Kernels to RISC-VR. StahlMykola Moshak
Crosstalk-Aware Topology Generation for Wavelength-Routed Optical Networks-on-ChipsT.-M. TsengMoyuan Xiao
Switch Design for Microfluidic Large-Scale IntegrationT.-M. TsengYanlu Ma
Wavelength-Routed Optical Network-on-Chip Router Design Using Parallel Switching ElementsT.-M. TsengZhidan Zheng
Ensuring control flow integrity against soft-errors for embedded applicationsU. SharifChaoqun Liang