Im folgenden finden Sie alle offenen studentischen Arbeiten unseres Lehrstuhls. Wir bieten Masterarbeiten, Bachelorarbeiten, Forschungspraxis, Ingeneurpraxis und interdisziplinäre Projekte an. Falls für Sie keine passende Arbeit angeboten wird, kontaktieren Sie bitte einen wissenschaftlichen Mitarbeiter. Über die Forschungsgebiete unseres Lehrstuhls können Sie sich unter Forschung informieren.

Bachelorarbeiten

Modeling of Embedded Peripherals

Algorithm Based Fault Tolerance for Embedded Case Studies

Semihosting for ETISS instruction set simulator

Exploring the relationship between weights and accuracy of neural networks

RISC-V Pooling Plug-In for Neural Networks

Masterarbeiten

Analysis Framework for a Performance Estimator of a VP

Impact of Waveform Propagation on SRAM Behavior and Timings

Algorithm Based Fault Tolerance for Embedded Case Studies

Control Flow Protection of Embedded SW

RISCV Multi-level Simulation Setup for Fast RTL Accurate Evaluation

Extending a RISC-V RTL Fault Injection Simulation to link Architectural Error Models with Micro-Architectural Faults

Improving Accuracy of Binary Neural Networks using Shifting Operations

Path Delay Prediction with Convolutional Neural Networks

Efficient ADC/DAC Designs for RRAM-based Neural Network Accelerators

Pruning Neural Networks with Classification Activation Paths

Exploring Robust Optical Accelerators for Neural Networks

Block-wise Training for Systolic Arrays of Digital Neural Network Accelerators

Automotive SoC Simulation Methodologies for ADAS Software Development Using QEMU and SystemC Simulators: RISC V/ARM

Automotive SOC Modeling using Host-Compiled Simulation and Timing Annotation Methods to Recover Software Execution Timings: RISC V/ARM

Neural Network Evaluation and Enhancement Considering Quantization

Neural Network Enhancement for Robustness of RRAM-based Design

Algorithm Development for 3D Automatic Routing

Non-Linear Weight Expansionfor Neural Networks

RISC-V Pooling Plug-In for Neural Networks

Interdisziplinäre Projekte

Modeling of Embedded Peripherals

Algorithm Based Fault Tolerance for Embedded Case Studies

ETISS CoreDSL 2.0 Code Generator

Forschungspraxis (Research Internship)

Analysis Framework for a Performance Estimator of a VP

Impact of Waveform Propagation on SRAM Behavior and Timings

Modeling of Embedded Peripherals

Algorithm Based Fault Tolerance for Embedded Case Studies

Control Flow Protection of Embedded SW

RISCV Multi-level Simulation Setup for Fast RTL Accurate Evaluation

Extending a RISC-V RTL Fault Injection Simulation to link Architectural Error Models with Micro-Architectural Faults

Ingenieurpraxis

Modeling of Embedded Peripherals

Algorithm Based Fault Tolerance for Embedded Case Studies

Implementation of a Switching Activity Estimator in the PyMTL3 Framework

Seminare

State of the art in Open Set Classification

State of the art in Open Set Classification

State of the art in Explainable AI & Interpretable AI

Uncertainty Estimation for Deep Learning PPA Regression

Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization

An Energy-Efficient Reconfigurable Nanophotonic Computing Architecture Design: Optical Lookup Table

Leakage Models for High-Level Power Estimation

Soft error resilience for tiny ML systems

SW Techniques for soft error resilience

SW Techniques for soft error resilience

Survey: Power Estimation on the Electronic System Level

Survey: Power Estimation on the Electronic System Level

Semihosting in instruction set simulators and virtual platforms

Performance Evaluation for RISC-V-based Virtual Prototypes

Sample Preparation for Microfluidic Platforms

A polynomial time optimal diode insertion/routing algorithm for fixing antenna problem

A general multi-layer area router

Semihosting in instruction set simulators and virtual platforms

A Survey on Hardware Monitoring Systems for Runtime Verification

A Survey on Resource Management Strategies for Many-Processors

Performance Comparison of Derivative Free Optimization Algorithms

Data Driven Analog Design Automation

Multi-Objective System-Level Optimization of Embedded Memory PPA

Transfer Learning for Embedded Memory PPA Regression

A polynomial time optimal diode insertion/routing algorithm for fixing antenna problem

A general multi-layer area router

Layout Decomposition for Triple Patterning Lithography

Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography

Automated Dimensioning of Networked Labs-on-Chip

Leakage Models for High-Level Power Estimation

An Energy-Efficient Reconfigurable Nanophotonic Computing Architecture Design: Optical Lookup Table

A monolithic single-chip point-of-care platform for metabolomic prostate cancer detection

Designing self-organized nanopatterns on Si by ion irradiation and metal co-deposition

Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization

FastRoute: a step to integrate global routing into placement

A Memetic Algorithm for VLSI Floorplanning

Studentische Hilfskräfte

Impact of Waveform Propagation on SRAM Behavior and Timings

ETISS CoreDSL 2.0 Code Generator