Bachelorarbeiten

Semihosting for ETISS instruction set simulator

Exploring the relationship between weights and accuracy of neural networks

Analog/Mixed-Signal Layout Design

RISC-V Pooling Plug-In for Neural Networks

Advanced Code Coverage Analysis for Embedded Software Development

Entwicklung einer STL-Bibliothek für das 3D-Drucken

Masterarbeiten

Advanced Implementation Methods of On-chip Performance Monitors

Neural Network Evaluation and Enhancement Considering Quantization

Neural Network Enhancement for Robustness of RRAM-based Design

Analog/Mixed-Signal Layout Design

Algorithm Development for 3D Automatic Routing

Static Code Analysis with C++

Non-Linear Weight Expansionfor Neural Networks

Efficient Implementation of Partial Operator Folding for Low-memory Implementation of Artificial Neural Networks on Embedded Microcontrollers

RISC-V Pooling Plug-In for Neural Networks

Advanced Code Coverage Analysis for Embedded Software Development

Virtual Prototyping of a Dual Microcontroller ECU (at Helbling)

Generation and development of processor cores for Virtual Prototypes (at Infineon)

Forschungspraxis (Research Internship)

Advanced Code Coverage Analysis for Embedded Software Development

Ingenieurpraxis

Semihosting for ETISS instruction set simulator

Seminare

Dyadic Neural Network Quantization

A Survey on Hardware Monitoring Systems for Runtime Verification

A Survey on Resource Management Strategies for Many-Processors

Performance Comparison of Derivative Free Optimization Algorithms

Data Driven Analog Design Automation

Multi-Objective System-Level Optimization of Embedded Memory PPA

Transfer Learning for Embedded Memory PPA Regression

A polynomial time optimal diode insertion/routing algorithm for fixing antenna problem

A general multi-layer area router

Layout Decomposition for Triple Patterning Lithography

Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography

Automated Dimensioning of Networked Labs-on-Chip

Leakage Models for High-Level Power Estimation

Graph Neural Networks in Electronic Design Automation

An Energy-Efficient Reconfigurable Nanophotonic Computing Architecture Design: Optical Lookup Table

A monolithic single-chip point-of-care platform for metabolomic prostate cancer detection

Designing self-organized nanopatterns on Si by ion irradiation and metal co-deposition

Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization

Global routing attached sequence pair for analog layout synthesis

FastRoute: a step to integrate global routing into placement

A Memetic Algorithm for VLSI Floorplanning