Im folgenden finden Sie alle offenen studentischen Arbeiten unseres Lehrstuhls. Wir bieten Masterarbeiten, Bachelorarbeiten, Forschungspraxis, Ingeneurpraxis und interdisziplinäre Projekte an. Falls für Sie keine passende Arbeit angeboten wird, kontaktieren Sie bitte einen wissenschaftlichen Mitarbeiter. Über die Forschungsgebiete unseres Lehrstuhls können Sie sich unter Forschung informieren.

Bachelorarbeiten

Semihosting for ETISS instruction set simulator

Exploring the relationship between weights and accuracy of neural networks

Analog/Mixed-Signal Layout Design

RISC-V Pooling Plug-In for Neural Networks

Masterarbeiten

Improving Accuracy of Binary Neural Networks using Shifting Operations

Path Delay Prediction with Convolutional Neural Networks

Efficient ADC/DAC Designs for RRAM-based Neural Network Accelerators

Pruning Neural Networks with Classification Activation Paths

Exploring Robust Optical Accelerators for Neural Networks

Block-wise Training for Systolic Arrays of Digital Neural Network Accelerators

Automotive SoC Simulation Methodologies for ADAS Software Development Using QEMU and SystemC Simulators: RISC V/ARM

Automotive SOC Modeling using Host-Compiled Simulation and Timing Annotation Methods to Recover Software Execution Timings: RISC V/ARM

Neural Network Evaluation and Enhancement Considering Quantization

Neural Network Enhancement for Robustness of RRAM-based Design

Analog/Mixed-Signal Layout Design

Algorithm Development for 3D Automatic Routing

Static Code Analysis with C++

Non-Linear Weight Expansionfor Neural Networks

Efficient Implementation of Partial Operator Folding for Low-memory Implementation of Artificial Neural Networks on Embedded Microcontrollers

RISC-V Pooling Plug-In for Neural Networks

Generation and development of processor cores for Virtual Prototypes (at Infineon)

Interdisziplinäre Projekte

ETISS CoreDSL 2.0 Code Generator

Forschungspraxis (Research Internship)

Comparison of Power Dissipation of FPGA and ASIC Implementations for ML Applications

Ingenieurpraxis

Implementation of a Switching Activity Estimator in the PyMTL3 Framework

Seminare

A polynomial time optimal diode insertion/routing algorithm for fixing antenna problem

A general multi-layer area router

A Survey on Resource Management Strategies for Many-Processors

A Survey on Hardware Monitoring Systems for Runtime Verification

Dyadic Neural Network Quantization

A Survey on Hardware Monitoring Systems for Runtime Verification

A Survey on Resource Management Strategies for Many-Processors

Performance Comparison of Derivative Free Optimization Algorithms

Data Driven Analog Design Automation

Multi-Objective System-Level Optimization of Embedded Memory PPA

Assertion-based Verification of Embedded Software through Model-driven Design

Transfer Learning for Embedded Memory PPA Regression

A polynomial time optimal diode insertion/routing algorithm for fixing antenna problem

A general multi-layer area router

Layout Decomposition for Triple Patterning Lithography

Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography

Automated Dimensioning of Networked Labs-on-Chip

Leakage Models for High-Level Power Estimation

Graph Neural Networks in Electronic Design Automation

An Energy-Efficient Reconfigurable Nanophotonic Computing Architecture Design: Optical Lookup Table

A monolithic single-chip point-of-care platform for metabolomic prostate cancer detection

Designing self-organized nanopatterns on Si by ion irradiation and metal co-deposition

Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization

FastRoute: a step to integrate global routing into placement

A Memetic Algorithm for VLSI Floorplanning

Studentische Hilfskräfte

ETISS CoreDSL 2.0 Code Generator