VHDL System Design Lab

Module Number: EI7403

Duration: 1 Semseter

Occurence: Winter/summer semester

Language: English

Number of ECTS: 6

Staff

Professor in charge: Ulf Schlichtmann

Amount of work

Contact hours: 60

Self-studying hours: 120

Total: 180

Description of achievement and assessment methods

Examination with the following elements:

• Oral examination (60%)
• Homework and projects: (40%)

Exam type: written

Exam duration: 60 min.

Possibility of re-taking: In the next semester: Yes; at the end of the semester: No

Homework: Yes

Lecture: No

Conversation: Yes

Written paper: Yes

Recommended requirements

Fundamentals of digital logic design; fundamentals of programming.

Contents

Design of a security IC using the HW description language VHDL: hierachical description of the encryption method on algorithmic and register-transfer level, implementation of test environments (test benches) using simulation to verify functionality and timing reference model in JAVA, insight into the internal steps of hardware synthesis, implementation on FPGA, FPGA design flow with industry-relevant tools, FPGA programming via USB, design test using a test program on PC.

Study goals

At the end of the module students are capable of designing a digital circuit in VHDL using industry-relevant design software. They are familiar with the usage of a hardware-oriented description language (VHDL) to describe and to design integrated circuits and systems.

Teaching and learning methods

• Learning method: In addition to the individual methods of the students consolidated knowledge is acquired by providing subtasks of increasing complexity and difficulty in the laboratory notes.
• Teaching method: Students are free to work on their own, according to their own scheudule on the laboratory tasks. Students can work on the labortaory either in institute rooms or at home. An advisor is available who will support them in case of siginificant difficulties.

Media formats

The following kinds of media are used:

• Introductory lectures
• Lecture slides available
• Laboratory notes with detailed descriptions of tasks and tool environments
• Individual discussions with advisor

Literature

The following literature is recommended:

• ANSI, IEEE Standards Board, IEEE Standard VHDL Language Reference Manual: IEEE std. 1076-1993, New York, 1988, ISBN 1559373768
• Peter J. Ashenden, Designer's Guide to VHDL, Morgan Kaufmann Publishers, 1995, ISBN 1558602704
• More literature listed in laboratory notes