Testing Digital Circuits

Lecturer (assistant)
Number0000004335
Type
Duration3 SWS
TermWintersemester 2020/21
Language of instructionEnglish
Position within curriculaSee TUMonline

Dates

Admission information

Objectives

At the end of the module students know about the following topics and are able to employ this knowledge to define and evaluate test solutions for digital ICs and systems: - Definition of testing and the difference to verification - Fundamentals of testing: fault models, fault detection, redundant faults, fault coverage - Methods for test generation: Boolean differences, D-algorithm, fault simulation - Analysis of test complexity with the help of complexity theory - Principles of passive test methods: Ad-hoc measures, scan path / Principles of active test methods: BIST - Overview over memory fault models and memory test algorithms. - Outline of test standards (IEEE boundary scan test) and additional topics like IDDQ testing, analog testing, fault analysis.

Description

29 Oct 2020: Due to the recent developments the course is switched to online! It is planned to offer the course in physical presence in WS 2020/21. The number of participants is therefore limited. Principles of testing digital circuits; fault models and test quality; functional and structural test generation; fault simulation; complexity theory; design for test (passive, active test methods); memory test; test standards; miscellaneous topics (Iddq test, analog test, test pattern compression, yield management); In detail: The manufacturing process of integrated circuits introduces a large variety of physical defects. In order to prevent the delivery of failing silicon devices to the customer, the correct function of delivered integrated circuits has to be guaranteed by testing all devices after they have been fabricated. Testing integrated circuits is one of the core competencies of a semiconductor company. It represents a significant factor in costs and quality. Therefore, testing is considered as an outstanding part of the entire design and manufacturing process of ICs. Furthermore, testing is a domain-crossing topic: The test engineer within a semiconductor company requires a broad expertise covering circuit and system design, circuit simulation and design verification, and physical design. One of the main challenges in testing is costs which have drastically increased over the past years. The access to circuit internal transistors and nodes has to be accomplished by a limited number of external pins. This is increasingly difficult due to the continuous shrinking of device structures. This lecture conveys: * The basic idea of testing. * Relevant failure mechanisms of integrated circuits and the common fault models. * The complexity problem of testing and its resulting limitations. * Methods for test pattern generation (e.g. fault simulation and automatic test generation). * Fundamental measures for designing integrated circuits in order to raise their testability (Design-for-Testability). * Techniques for insertion of built-in self-test (BIST) in integrated circuits. * Techniques for memory testing.

Prerequisites

Basics of digital circuit design. The following modules should be passed before taking the course: - Digital IC-Design - Electronic Design Automation

Teaching and learning methods

Learning method: In addition to the individual methods of the students consolidated knowledge is aspired by repeated lessons in exercises and tutorials. Teaching method: During the lectures students are instructed in a teacher-centered style. The exercises are held in a student-centered way. Where applicable, each of the 10 chapters of the lectures is immediately followed by an associated exercise/tutorial block.

Examination

The examination will be in an oral, highly interactive and dynamic form. The student will show his/her ability to understand, apply, develop and evaluate test solutions for digital integrated circuits and systems, at the concrete example of a small digital circuit with single stuck-at faults. In detail, he/she will compute test patterns and develop parts of a scan path and of a built-in self-test. While doing so, the student will present his/her understanding of the underlying algorithms and methods, as there are e.g. D-algorithm, test complexity analysis, IEEE 1149.1 boundary scan testing, memory testing, IDDQ testing.

Recommended literature

The following literature is recommended: * Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits; M. Bushnell, V. Agrawal; Kluwer Academic Publishers, 2000. * Digital Systems Testing and Testable Design; M. Abramovici, M. Breuer, A. Friedmann; Computer Science Press, 1990

Links


All courses

Bachelorbereich: BSc-EI, MSE, BSEEIT

 

WS

SS

Diskrete Mathematik für Ingenieure (BSEI, EI00460)

Discrete Mathematics for Engineers (BSEEIT) (Schlichtmann) (Januar)

 

O

WS

SS

Entwurf digitaler Systeme mit VHDL u. System C (BSEI, EI0690) (Ecker)

WS 20/21 block course after lecture period

P

 

SS

Entwurfsverfahren für integrierte Schaltungen (MSE, EI43811) (Schlichtmann)

 

WS

 

Methoden der Unternehmensführung (BSEI, EI0481) (Weigel)

O

WS

 

Praktikum System- und Schaltungstechnik (BSEI, EI0664) (Schlichtmann et al.)

?

 

SS

Schaltungssimulation (BSEI, EI06691) (Gräb/Schlichtmann)

 

 

Masterbereich: MSc-EI, MSCE, ICD

 

SS

Advanced Topics in Communication Electronics (WS20/21: Willy Sansen) (MSCE, MSEI, EI79002)

P

WS

 

Aspects of Integrated Systems Technology & Design (MSCE, MSEI, EI5013) (Wurth)

fällt aus

WS

 

Electronic Design Automation (MSCE, MSEI, EI70610) (B. Li, Tseng)

O

WS

 

Design Methodology and Automation (ICD) (Schlichtmann) (Nov)

 

WS

SS

Machine Learning: Methods and Tools (MSCE, MSEI, EI71040) (Ecker)

O

WS

SS

SS

Mathematical Methods of Circuit Design (MSCE, MSEI, EI74042) (Gräb)

Simulation and Optimization of Analog Circuits (ICD) (Gräb) (Mai)

O+P

WS

 

Mixed Integer Programming and Graph Algorithms in Engineering Problems (MSCE, MSEI, EI71059) (Tseng)

O

WS

SS

Numerische Methoden der Elektrotechnik (MSEI, EI70440) (Diepold oder Schlichtmann)

O

WS

WS

SS

Seminar VLSI-Entwurfsverfahren (MSEI, EI7750) (Schlichtmann/Müller-Gritschneder)

Seminar on Topics in Electronic Design Automation (MSCE, EI77502) (Schlichtmann/Müller-Gritschneder)

O P?

O

WS

SS

Synthesis of Digital Systems (MSCE, MSEI, EI70640) (Müller-Gritschneder)

O

WS

 

Testing Digital Circuits (MSCE, MSEI, EI50141) (Otterstedt)

P

WS

 

Timing of Digital Circuits (MSCE, MSEI, EI70550) (B. Li, Zhang)

O

WS

SS

VHDL System Design Laboratory (MSCE, MSEI, EI7403) (Schlichtmann)

O

WS

SS

VLSI Design Laboratory (MSCE, MSEI, EI5043) (Schlichtmann)

fällt aus

 

The right-most column describes the planned type of lecture in the winter term 2020/21 - assuming that lecture halls are available: O=online, P=presence

 

MSE: Munich School of Engineering (TUM)
BSEEIT: Bachelor in Electrical Engineering and Information Technology (TUM-Asia)
ICD: Master of Science in Integrated Circuit Design (TUM-Asia)
MSCE: Master of Science in Communications Engineering (TUM)

MSEI: Master of Science in Elektrotechnik und Informationstechnik

BSEI: Bachelor of Science in Elektrotechnik und Informationstechnik

 

Please keep yourself updated at https://www.tum.de/die-tum/aktuelles/coronavirus/studium/ and www.ei.tum.de for updated information about teaching.