Seminar on Topics in Electronic Design Automation
|Language of instruction||English|
|Position within curricula||See TUMonline|
- 09.11.2020 16:45-18:15 4905, Seminarraum, Will be held as an online event.
- 23.11.2020 16:45-18:15 4905, Seminarraum, Will be held as an online event.
- 07.12.2020 16:45-18:15 4905, Seminarraum, Will be held as an online event.
- 28.01.2021 09:00-17:00 4905, Seminarraum, Will be held as an online event.
- 29.01.2021 09:00-17:00 4905, Seminarraum, Will be held as an online event.
Note: Students have to choose a seminar topic before the introduction lesson. You need to contact a supervisor of a topic you are interested in. Topics are selected on a first come first served basis. You will be registered for the seminar after your topic supervisor has confirmed your chosen topic. For a list of topics refer to the following links: http://www.eda.ei.tum.de/index.php?id=173).
Teaching and learning methods
Please find the topics for the WT 20/21 below.
The topics are handed out on a first-come-first served basis. Contact the supervisor of the topic to get more information and reserve a topic. Please make sure, that you get a confirmation of your supervisor onlce you selected a topic. We are looking forward to see you in the seminar.
|4 topics on Bayesian optimization and layout in analog design||H. Gräb||Analog EDA|
|Examining security issues in neuromorphic computing||B. Li|
|Examining timing in all EDA steps||B. Li|
|State-of-the-Art Methods for Performance Determination in Industrial Microcontrollers||C. Foik|
|Semihosting in instruction set simulators and virtual platforms||K. Emrich|
|Reservation-based Scheduling||M. Mettler|
|Runtime Requirements Enforcement Techniques on Embedded Systems||M. Mettler|
|A Device Non-Ideality Resilient Approach for Mapping Neural Networks to Crossbar Arrays||S. Zhang|
|ReSiPE: ReRAM-based Single-Spiking Processing-In-Memory Engine||S. Zhang|
|Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks||T.-M. Tseng|
|Dilution and Mixing Algorithms for Flow-Based Microfluidic Biochips||T.-M. Tseng|
|A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference||Y. Chuang|
|Neural networks on microcontrollers: saving memory at inference via operator reordering||Y. Chuang|
|Automated Dimensioning of Networked Labs-on-Chip||Y. Moradi|
|Automatic Software Self-Healing Using Rescue Points||Y. Moradi|
|Extension of Embedded Processor Instruction Sets||Y. Moradi|
|Efficient Processing of Deep Neural Networks: A Tutorial and Survey||Li Zhang||Elmas Kamil Cankut|
|HAQ: Hardware-Aware Automated Quantization with Mixed Precision||Li Zhang||Venkata Prasanna Kumar|
|Path Predicate Abstraction: System-Level Modeling for Correct-by-Construction RTL Designs||C. Foik||Sanchita Vishwa|
|A Unified Property Specification Language for HW/SW Co-Verification||C. Foik||Ebru Avci|
|Performance simulation for instruction set simulators||K. Emrich||Shreya Morgansgate|
|Advanced Simulation of Quantum Computations||M. Li||Toniolo Nicolò|
|Crosstalk Noise in WDM-Based Optical Networkson- Chip: A Formal Study and Comparison||M. Li||Deshmukh, Girija Sandeep|
|Dynamically Scheduled High-level Synthesis||Y. Moradi||Jiahui Xu|