Offered Theses

TopicAssistentArea
Procedural Analog Module Generation with State of the Art ToolsH. GräbAnalog EDA
Integration of feedback structure in an automatic initial sizing toolI. AbelAnalog EDA
Multiplier and Adder Analysis and Characterization for Neural Networks B. LiDigital Design
Countering Probing of Digital Circuits with Sensitive TimingB. LiDigital Design
Security of Systolic Array Implementation of Neural NetworksB. LiDigital Design
Internship Digital VerificationH. GräbDigital Design
Robustness Enhancement of Neural Networks Li ZhangDigital Design
Virtual Prototyping of a Dual Microcontroller ECU (at Helbling)C. FoikHigh-Level Modeling
Advanced RISC-V ISS Coverage Metrics Solutions (at MinRES)D. Müller-G.High-Level Modeling
Timing Models for Ultra-fast Host-compiled Simulation of Embedded SoftwareD. Müller-G.High-Level Modeling
Automated Generation of Integration Tests for Functional Verification of Instruction Set Simulators J. GeierHigh-Level Modeling
Test Coverage Solutions for Test-Driven Software DevelopmentY. MoradiHigh-Level Modeling
Stellenausschreibung Deutsches PatentamtH. Gräb
Using solutions of an automatic initial sizing tool to seed optimizations in WiCkeDI. Abel
Area-efficient Optical Neural NetworksLi Zhang
Control-flow extensions to RISC-V ISA for accelerated Neural Network inferenceR. Stahl
Efficient Implementation of Partial Operator Folding for Low-memory Implementation of Artificial Neural Networks on Embedded MicrocontrollersR. Stahl
RISC-V Instruction Set Extension for Activation Functions of Neural Networks R. Stahl
Static Code Analysis Topics with C++R. Stahl
Various Topics with our Open-Source Simulator ETISS (C++)R. Stahl
RTL Accurate Fault Injection for RISC-V SoCsU. Sharif
Topics on Flow-Based Microfluidic Biochips for Single-Cell Analysis (C++ or Python)Y. Moradi

Just contact a research assistant, if you are interested in a topic not listed here.

Assigned Theses

TopicAssistentStudent
Extension of an automatic initial sizing tool for analog circuits to support three stage op ampsI. Abelreserved
Implementing the Gm/Id-Methode in an automatic sizing tool for analog circuitsI. Abelreserved
Design and Optimization of Rail-to-Rail OpAmpsM. NeunerEileen Haardt
Test Generation for Digital Circuits with Wave-PipeliningB. LiOngoing
Development of a Virtual Prototype of a security RISC-V System on Chip D. Müller-G.Andrea Lardschneider
Automated Test Coverage Analysis for Test-Driven Software Development using ETISSY. MoradiPhilipp Fengler
TDD of Hardware-Near Software on the Instruction Set Simulator ETISSC. FoikYasal Imran
Development of a Modular Monitoring Architecture for Large-scale MPSoCsM. MettlerPhilip Grill
Partial Reconfiguration of Runtime Monitors on FPGAsM. MettlerWaqas Ahsan
Discrete Optimization of Analog CircuitsM. NeunerMalek M'Hiri
Adding a Language Frontend to an ISA Code Generator ToolR. StahlNina Mutzel
Porting Neural Network Software Kernels to RISC-VR. StahlMykola Moshak
Crosstalk-Aware Topology Generation for Wavelength-Routed Optical Networks-on-ChipsT.-M. TsengMoyuan Xiao
Switch Design for Microfluidic Large-Scale IntegrationT.-M. TsengYanlu Ma
Wavelength-Routed Optical Network-on-Chip Router Design Using Parallel Switching ElementsT.-M. TsengZhidan Zheng
Ensuring control flow integrity against soft-errors for embedded applicationsU. SharifChaoqun Liang