Offered Theses

Topic	Assistent	Area
Procedural Analog Module Generation with State of the Art Tools	H. Gräb	Analog EDA
Integration of feedback structure in an automatic initial sizing tool	I. Abel	Analog EDA
Multiplier and Adder Analysis and Characterization for Neural Networks	B. Li	Digital Design
Countering Probing of Digital Circuits with Sensitive Timing	B. Li	Digital Design
Security of Systolic Array Implementation of Neural Networks	B. Li	Digital Design
Internship Digital Verification	H. Gräb	Digital Design
Robustness Enhancement of Neural Networks	Li Zhang	Digital Design
Virtual Prototyping of a Dual Microcontroller ECU (at Helbling)	C. Foik	High-Level Modeling
Advanced RISC-V ISS Coverage Metrics Solutions (at MinRES)	D. Müller-G.	High-Level Modeling
Timing Models for Ultra-fast Host-compiled Simulation of Embedded Software	D. Müller-G.	High-Level Modeling
Automated Generation of Integration Tests for Functional Verification of Instruction Set Simulators	J. Geier	High-Level Modeling
Test Coverage Solutions for Test-Driven Software Development	Y. Moradi	High-Level Modeling
Stellenausschreibung Deutsches Patentamt	H. Gräb
Using solutions of an automatic initial sizing tool to seed optimizations in WiCkeD	I. Abel
Area-efficient Optical Neural Networks	Li Zhang
Control-flow extensions to RISC-V ISA for accelerated Neural Network inference	R. Stahl
Efficient Implementation of Partial Operator Folding for Low-memory Implementation of Artificial Neural Networks on Embedded Microcontrollers	R. Stahl
RISC-V Instruction Set Extension for Activation Functions of Neural Networks	R. Stahl
Static Code Analysis Topics with C++	R. Stahl
Various Topics with our Open-Source Simulator ETISS (C++)	R. Stahl
RTL Accurate Fault Injection for RISC-V SoCs	U. Sharif
Topics on Flow-Based Microfluidic Biochips for Single-Cell Analysis (C++ or Python)	Y. Moradi

Just contact a research assistant, if you are interested in a topic not listed here.

Assigned Theses

Topic	Assistent	Student
Extension of an automatic initial sizing tool for analog circuits to support three stage op amps	I. Abel	reserved
Implementing the Gm/Id-Methode in an automatic sizing tool for analog circuits	I. Abel	reserved
Design and Optimization of Rail-to-Rail OpAmps	M. Neuner	Eileen Haardt
Test Generation for Digital Circuits with Wave-Pipelining	B. Li	Ongoing
Development of a Virtual Prototype of a security RISC-V System on Chip	D. Müller-G.	Andrea Lardschneider
Automated Test Coverage Analysis for Test-Driven Software Development using ETISS	Y. Moradi	Philipp Fengler
TDD of Hardware-Near Software on the Instruction Set Simulator ETISS	C. Foik	Yasal Imran
Development of a Modular Monitoring Architecture for Large-scale MPSoCs	M. Mettler	Philip Grill
Partial Reconfiguration of Runtime Monitors on FPGAs	M. Mettler	Waqas Ahsan
Discrete Optimization of Analog Circuits	M. Neuner	Malek M'Hiri
Adding a Language Frontend to an ISA Code Generator Tool	R. Stahl	Nina Mutzel
Porting Neural Network Software Kernels to RISC-V	R. Stahl	Mykola Moshak
Crosstalk-Aware Topology Generation for Wavelength-Routed Optical Networks-on-Chips	T.-M. Tseng	Moyuan Xiao
Switch Design for Microfluidic Large-Scale Integration	T.-M. Tseng	Yanlu Ma
Wavelength-Routed Optical Network-on-Chip Router Design Using Parallel Switching Elements	T.-M. Tseng	Zhidan Zheng
Ensuring control flow integrity against soft-errors for embedded applications	U. Sharif	Chaoqun Liang