Offered Theses

Topic	Assistent	Area
Development of a Virtual Test Environment for Hardware-Near Software: Various Tasks	C. Foik	High-Level Modeling
Virtual Prototyping of a Dual Microcontroller ECU (at Helbling)	C. Foik	High-Level Modeling
Advanced RISC-V ISS Coverage Metrics Solutions (at MinRES)	D. Müller-G.	High-Level Modeling
Timing Models for Ultra-fast Host-compiled Simulation of Embedded Software	D. Müller-G.	High-Level Modeling
Advanced Code Coverage Analysis for Embedded Software Developement	Y. Moradi	High-Level Modeling
Hardware accelerators based on digital logic and emerging devices for deep neural networks	Li Zhang
Neural network architectures	Li Zhang
Security of hardware implementation of neural networks	Li Zhang
Efficient Implementation of Partial Operator Folding for Low-memory Implementation of Artificial Neural Networks on Embedded Microcontrollers	R. Stahl
Machine Learning on Microcontrollers: Exploring Radar Use Case	R. Stahl
Non-Linear Weight Expansion for Neural Networks	R. Stahl
RISC-V Pooling Plug-In for Neural Networks	R. Stahl
Static Code Analysis Topics with C++	R. Stahl

Just contact a research assistant, if you are interested in a topic not listed here.

Assigned Theses

Topic	Assistent	Student
Development of a Virtual Prototype of a security RISC-V System on Chip	D. Müller-G.	Andrea Lardschneider
Automated Test Coverage Analysis for Test-Driven Software Development using ETISS	Y. Moradi	Philipp Fengler
RTL Accurate Fault Injection for RISC-V SoCs	U. Sharif	Xubin Wang
Sihft development for soft-errors for embedded applications	U. Sharif	Chaoqun Liang, Yicheng Qiu, Simon Jarc