Offered Theses

Development of a Virtual Test Environment for Hardware-Near Software: Various TasksC. FoikHigh-Level Modeling
Virtual Prototyping of a Dual Microcontroller ECU (at Helbling)C. FoikHigh-Level Modeling
Advanced RISC-V ISS Coverage Metrics Solutions (at MinRES)D. Müller-G.High-Level Modeling
Timing Models for Ultra-fast Host-compiled Simulation of Embedded SoftwareD. Müller-G.High-Level Modeling
Advanced Code Coverage Analysis for Embedded Software DevelopementY. MoradiHigh-Level Modeling
Hardware accelerators based on digital logic and emerging devices for deep neural networksLi Zhang
Neural network architecturesLi Zhang
Security of hardware implementation of neural networksLi Zhang
Efficient Implementation of Partial Operator Folding for Low-memory Implementation of Artificial Neural Networks on Embedded MicrocontrollersR. Stahl
Machine Learning on Microcontrollers: Exploring Radar Use CaseR. Stahl
Non-Linear Weight Expansion for Neural NetworksR. Stahl
RISC-V Pooling Plug-In for Neural NetworksR. Stahl
Static Code Analysis Topics with C++R. Stahl

Just contact a research assistant, if you are interested in a topic not listed here.

Assigned Theses

Development of a Virtual Prototype of a security RISC-V System on Chip D. Müller-G.Andrea Lardschneider
Automated Test Coverage Analysis for Test-Driven Software Development using ETISSY. MoradiPhilipp Fengler
RTL Accurate Fault Injection for RISC-V SoCsU. SharifXubin Wang
Sihft development for soft-errors for embedded applicationsU. SharifChaoqun Liang, Yicheng Qiu, Simon Jarc