Offered Theses

Internship Digital VerificationH. GräbDigital Design
Automated Generation of Integration Tests for Functional Verification of Instruction Set Simulators J. GeierHigh-Level Modeling
Using solutions of an automatic initial sizing tool to seed optimizations in WiCkeDI. Abel
Various Topics with our Open-Source Simulator ETISS (C++)R. Stahl
Booting FreeRTOS on EDA's ETISS simulatorU. Sharif
Regression testing / continuous integration for feature development on ETISS simulatorU. Sharif
Various topics on fault injection data analysisU. Sharif
Data Base Integration for an Instruction Set SimulatorY. Moradi
Testing Transposer-Based Microfluidic Routing FabricY. Moradi
Topics on Flow-Based Microfluidic Biochips for Single-Cell Analysis (C++ or Python)Y. Moradi

Just contact a research assistant, if you are interested in a topic not listed here.

Assigned Theses

Implementation of the EKV transistor model in an automatic initial sizing tool for analog circuitsI. AbelDeyan Wang
Dynamic code coverage analysis with ETISSY. MoradiPhilipp Fengler
Machine Learning Methods to Solve Timing Issues in Digital CircuitsB. LiOngoing
Architecture Exploration of Optical Neural NetworkLi ZhangAssigned
Automatic Router Design for Large-Scale Wavelength-Routed Optical NoCsT.-M. TsengQingyu Li
Bandwidth Optimization for Wavelength-Routed Optical Network-on-ChipT.-M. TsengWei Zhao
Design Space Exploration Considering MRR On/Off Feature for ONoCsT.-M. TsengSubarnaduti Paul
Various topics on SystemC based VP developmentU. SharifPhilip Dachs
Virtual prototyping of realistic embedded applicationsU. SharifYuang Xu, Philip Dachs