I research fault-tolerant Network on Chips (NoC) for safety-critical real-time systems. I especially focus on Time-Division Multiplexed (TDM) and hybrid NoCs.
SystemC Laboratory (since WS 2016/17)
Theses in my field of research might be possible even if they are not explicitly listed here. Feel free to contact me if you have an idea!
- Design and Implementation of a Network Interface for a Fault-Tolerant Hybrid Network on Chip
(Master Thesis, Alexander Ostertag, 2019)
- Design and Implementation of a Fault-Tolerant Control and Management Network for System on Chip
(Master Thesis, Daniel Padva, 2019)
- Development of a Monitoring and Fault Injection Module for a Hybrid NoC
(Bachelor Thesis, Laura Grünauer, 2019)
- Design and Implementation of an IO-Tile for an MPSoC Demonstrator on a FPGA
(Research Internship, Lorenz Völk, 2019)
- Implementation of Fault-Injection & Fault-Detection Mechanisms in a Time-Division Multiplexed Network on Chip
(Research Internship, Andrea Nicholas Beretta, 2019)
- Implementation and Evaluation of a UART Device Emulation Module
(Bachelor Thesis, Thomas Leyk, 2018)
- ARAMiS II
Researching the utilization of multi-core systems in safety-critical applications. Funded by the german BMBF.
Open Source Projects
- Multi-Objective Optimization of Channel Mapping for Fail-Operational Hybrid TDM NoCs. 2019 Seventh International Symposium on Computing and Networking (CANDARW), 2019 more… BibTeX
- A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC. ARCS Konferenz, 2019 more… BibTeX Full text ( DOI )
- Channel Mapping Strategies for Effective Protection Switching in Fail-Operational Hard Real-Time NoCs. Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2019 more… BibTeX Full text ( DOI )