I research fault-tolerant Network on Chips (NoC) for safety-critical real-time systems. I especially focus on Time-Division Multiplexed (TDM) and hybrid NoCs.
Feature Improvements for an MPSoC Demonstrator System
Description
Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift towards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel. To demonstrate the abilities of a hybrid NoC with protection switching for critical traffic, an MPSoC demonstrator system was developed at LIS.
Goal:
The goal of this work is to implement and integrate various improvements to the existing demonstrator system—particularly the GUI and the software backend—in order to improve performance, stability, and enable new features.
Prerequisites
To successfully complete this project, you should already have the following skills and experiences:
Good Python programming skills and knowledge in OOP
At least basic Javascript programming skills
Basic knowledge of embedded systems architecture
Self-motivated and structured work style
Learning Objectives:
By completing this project, you will be able to:
Comfortably develop applications on different layers of the software stack
Adopt software to interface with and utilize hardware modules
Document your work in form of a scientific report and a presentation
Random number generation (RNG) is an essential part of many applications, be it for encryption, testing, or other purposes. However, randomness is difficult to accomplish in digital circuits which are supposedly deterministic.
The goal of this seminar topic is to understand and explain the challenges of RNG in hardware, and to compare different true random number generation (TRNG) and pseudo random number generation (PRNG) methods that are suitable for implementation on FPGA.
Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift towards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel. To demonstrate the abilities of a hybrid NoC with protection switching for critical traffic, an MPSoC demonstrator system was developed at LIS.
yle="mso-bidi-font-weight: normal;">Goal:
The goal of this work is to implement and integrate various improvements to the existing demonstrator system to improve performance, stability, and enable new features.
Prerequisites
To successfully complete this project, you should already have the following skills and experiences:
Good programming skills in a hardware description language i.e. VHDL or (System)Verilog
Design and Implementation of a Network Interface supporting Remote DMA for a Fault-Tolerant Hybrid Network on Chip (Master Thesis, Maximilian Ehm, 2020)
Design and Implementation of a Statistics Surveillance Module for an MPSoC Demonstrator System (Research Internship, Adrian Schiechel, 2020)
Implementation of a Pedestrian Detection Algorithm for a Fail-Operational Demonstrator System (Bachelor Thesis, Simon Webhofer, 2020)
Design and Implementation of a Traffic Generator Module for a Hybrid Network on Chip (Research Internship, Laura Grünauer, 2020)
Design and Implementation of a Network Interface for a Fault-Tolerant Hybrid Network on Chip (Master Thesis, Alexander Ostertag, 2019)
Design and Implementation of a Fault-Tolerant Control and Management Network for System on Chip (Master Thesis, Daniel Padva, 2019)
Development of a Monitoring and Fault Injection Module for a Hybrid NoC (Bachelor Thesis, Laura Grünauer, 2019)
Design and Implementation of an IO-Tile for an MPSoC Demonstrator on a FPGA (Research Internship, Lorenz Völk, 2019)
Implementation of Fault-Injection & Fault-Detection Mechanisms in a Time-Division Multiplexed Network on Chip (Research Internship, Andrea Nicholas Beretta, 2019)
Implementation and Evaluation of a UART Device Emulation Module (Bachelor Thesis, Thomas Leyk, 2018)
Projects
Research Projects
ARAMiS II Researching the utilization of multi-core systems in safety-critical applications. Funded by the german BMBF.
Open Source Projects
OpTiMSoC A free and open framework for tiled manycore SoCs
GLIP: the Generic Logic Interfacing Library Simple, FIFO-based communication between FPGA and a PC
Publications
Max Koenen, Nguyen Anh Vu Doan, Thomas Wild, and Andreas Herkersdorf: Exploring Task and Channel Mapping Strategies in Fail-Operational and Hard Real-Time NoCs. IEEE Nordic Circuits and Systems Conference (NorCAS 2020), 2020 more…BibTeX
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Nguyen Anh Vu Doan, Max Koenen, Thomas Wild, Andreas Herkersdorf: Multi-Objective Optimization of Channel Mapping for Fail-Operational Hybrid TDM NoCs. 2019 Seventh International Symposium on Computing and Networking (CANDARW), 2019 more…BibTeX
Max Koenen, Nguyen Anh Vu Doan, Thomas Wild, and Andreas Herkersdorf: A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC. ARCS Konferenz, 2019 more…BibTeX
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Max Koenen, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf: Channel Mapping Strategies for Effective Protection Switching in Fail-Operational Hard Real-Time NoCs. Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2019 more…BibTeX
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