Akshay Srivatsa, M.Sc.

Research Associate

Technische Universität München
Department of Electrical and Computer Engineering
Chair of Integrated Systems
Arcisstr. 21
80290 München

Phone: +
Fax: +
Building: N1 (Theresienstr. 90)
Room: N2140
Email: srivatsa.akshay@tum.de


Project Laboratory IC Design (WS 2018-19)

System-on-Chip Platforms (Since SS 2016)

Offered Work

Interested in an internship or a thesis? Please send me an email.
The given type of work is just a guideline and could be changed if needed.
From time to time, there might be some work, that is not announced yet. Feel free to ask!

Ongoing Work

Master's Theses

Evaluating Shared Memory Workloads on a DSM-based MPSoC using Region Based Cache Coherence

Exploring Hybrid Replacement Policies for Caches on an FPGA Prototype

Supervised Theses

  • Exploring a Hybrid Voting-based Eviction Policy for Last Level Caches
    (Master Thesis, Sebastian Nagel, 2020)
  • Exploring a Hybrid Cache Eviction Policy using Gem5
    (Leonardo Davinci Darwin, Research Internship, 2020)
  • Design and Implementation of a Coherence-Barrier for RBCC on an FPGA Prototype
    (Mostafa Mansour, Research Internship, 2020)
  • A Hardware Mechanism with Detect and Resolve False- Sharing for Region-Based Cache Coherence
    (Li-Yu Peng, Research Internship, 2020)
  • Extension of RBCC to DDR and Evaluation of Sparse Directory Eviction Policies
    (Research Internship, Miguel Montoya Rendon, 2019)
  • Runtime Rre-configuration of Region-Based Cache Coherence for DSM-based MPSoCs
    (Master Thesis, Sai Varun Brahmadevara, 2019)
  • High Level Simulation of a Smart Eviction Policy for Caches
    (Research Internship, Stephen Bullock, 2019)
  • A Hardware Mechanism to Detect & Resolve False-Sharing for Region-based Cache Coherence
    (Research Internship, Mohamed Gaith, 2019)
  • Compact Directories with Hybrid Architecture Aware Eviction Policies for Distributed Shared Memory MPSoCs
    (Master Thesis, Nael Fasfous, 2018)
  • Optimizing Cache Coherence for MPSoCs with Distributed Shared Memories using a High Level Simulation Model
    (Master Thesis, Yifang Wang, 2018)
  • Accelerated Cache Coherence for the InvasIC Architecture
    (Research Internship, Yifang Wang, 2016)
  • High Level Modelling of the InvasIC Architecture using Gem5
    (Working Student, Mengyu Liang, 2016)


  • Sven Rheindt, Srivatsa Akshay, Oliver Lenke, Lars Nolte, Thomas Wild, Andreas Herkersdorf: Tackling the MPSoC Data Locality Challenge. In: Multi-Processor System-on-Chip. ISTE Editions , 2020 more… BibTeX
  • Akshay Srivatsa, Sven Rheindt, Dirk Gabriel, Thomas Wild, Andreas Herkersdorf: CoD: Coherence-on-Demand - Runtime Adaptable Working Set Coherence for DSM-based Manycore Architectures. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIX) , 2019 more… BibTeX
  • Sven Rheindt, Andreas Schenk, Akshay Srivatsa, Thomas Wild, Andreas Herkersdorf: CaCAO: Complex and Compositional Atomic Operations for NoC-based Manycore Platforms. ARCS 2018 - 31st International Conference on Architecture of Computing Systems, 2018 more… BibTeX
  • Leonard Masing, Akshay Srivatsa, Fabian Kress, Nidhi Anantharajaiah, Andreas Herkersdorf, Juergen Becker: In-NoC-circuits for low-latency cache coherence in distributed shared-memory architectures. 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018 more… BibTeX
  • Akshay Srivatsa, Sven Rheindt, Thomas Wild, Andreas Herkersdorf: Region Based Cache Coherence for Tiled MPSoCs. 2017 30th IEEE International System-on-Chip Conference (SOCC), 2017 more… BibTeX