Learning classifier systems are a paradigm of rule-based machine learning methods that combine the power of a discovery component like genetic algorithms with a learning component like Q-learning. XCS is a type of LCS based on accuracy of the rules instead of strength, in order to achieve a rule-set with accurage and general rules to cover the input space. 

Ruleset reduction algorithms are used to reduce the size of the final ruleset. This work surveys the different types of ruleset reduction algorithms.

anmol.surhonne@tum.de

The main bottleneck in low-power DNN acceleration is data movement between processing elements and memory levels,  which accounts for nearly as 70% of the total energy budget, excluding the clock network. In recent years, different computer architectures such as logic-in-memory or brain-inspired computing, have been proposed, overcoming some of the limitations of the Von-Neumann architecture (memory wall), but introducing new problems in the synthesis of such systems. Neuromorphic computing [Loihi, TrueNorth] is a promising approach to achieve high energy efficiency, mixing analog/digital processing elements in VLSI systems. The candidate should investigate the theoretical aspects and applications of neuromorphic computing (digital), focusing on DNN acceleration.

Convolutional neural networks (CNNs) present many computation and memory challenges for embedded devices. An effective way to reduce the complexity of a CNN is by binarizing the weights and activations of the network. This drastically decreases the size of the CNN and results in XNOR-popcount operations replacing the standard Multiply-Accumulate operations, typically performed billions of times over the course of a single inference. However, binary neural networks (BNNs) are difficult to train and can lead to a severe degradation in accuracy. To effectively train BNNs, special methods are typically applied to help gradients flow during backpropagation through the non-differentiable functions employed in the forward pass. Other researchers have completely re-invented the training approach to accomodate the complexity of BNN training.

Adversarial attacks present a threat to convolutional neural networks deployed in real-time critical applications, such as autonomous driving. These attacks can be performed on the target classifier in the form of black box or white box attacks. In the second case, the attacker may transfer a generalized attack from one network to another. These attacks have been well studied for CNNs applied to 2D classifiers. In this seminar, the extended effect of these attacks on 3D classifiers will be studied.

Convolutional neural network (CNN) compression has become a standard approach of optimization before real-world deployment. Particularly in embedded scenarios, a high-accuracy CNN is usually heavily overparametrized for the target device. The most common techniques to compress a pretrained neural network are quantization and pruning. However, both techniques can also be applied at training-time, saving GPU hours and leading to one-shot training and optimization of CNNs.

Convolutional neural networks present many computational challenges which can be tackled through intelligent hardware design. However, with the increasing complexity of the hardware, it becomes difficult for a human designer to choose the correct hyperparameters of the processing and memory elements, before synthesis and fabrication. This is particularly the case, if the deployment neural network is not fixed at the time of designing the hardware. In this seminar, methods which apply metaheuristics to the problem of designing inferences hardware for CNNs will be studied.

Modern neural networks present a challenge in computational complexity on embedded platforms. However, their structures can offer a wide range of data reuse opportunities to reduce the cost of on-chip data movement. These reuse opporunities can be exploited through different dataflows. Convolutional neural network layers can be diverse in their dimensions and their execution style (depthwise, pointwise, dilated, etc.), making some reuse opportunties more attractive than others, depending on the the properties of the layer. For an embedded hardware to make use of all the possible reuse opportunities, a flexible on-chip interconnect is necessary, which is able to change the flow of execution at runtime.

Going beyond the efficient inference libraries provided by NVIDIA, researchers have started developing customized kernels, which better exploit their applied neural network compression techniques. In this seminar, these computation kernels will be studied and analyzed for the benefits they could offer to binary and sparse neural network execution.

LSTM neural networks are widely used for forecasting time-series data. Such forecasting capabilities can have applications in run-time management of embedded systems. However, in such use cases run-time inference overhead becomes critical. One method to minimize overhead is to reduce the number of input features of the LSTM neural network while preserving forecasting accuracy. The goal of this seminar is to review and compare the state-of-the-art in feature selection methodologies for LSTM neural networks.

This seminar topic should give an overview about the mathematic basics (Markov decision process) of multistep learning with LCSs.

flo.maurer@tum.de

LCS, especially XCS, have been shown to be effective for design space exploration.

Recently they have been applied to control problems more often.

Hereby, it's important to consider if the learning is applied online / while execution or offline / before execution.

flo.maurer@tum.de

Network Interface Controllers (NICs) are devices required to establish a connection between a computer and a network. While in most consumer devices, the NIC has meanwhile been integrated into the main board, Network Interface Cards remain an important expansion in e.g. server systems, where high throughputs have to be supported with certain quality of service contraints, and where NICs are still deployed as discrete devices. In order to efficiently distribute incoming data packets to the processing cores of their host systems, NICs make use of a variety of different load balancing techniques, like Receive Side Scaling (RSS). The goal of this seminar topic is to provide an overview over different load balancing approaches deployed in modern Netword Interface Cards, and to compare their advatages and drawbacks.

Data base systems are usually tasked with providing a specific set of data for a given index value. Because of large amounts of data stored in them, and because of size or performance constraints, realizing a 1:1 mapping is often not feasible or preferable. To overcome this problem, so-called hash functions are often applied to the index values, algorithms mapping a large set of possible input values to a comparatively small set of output values which can then be used to index the data base. As a result, the latter can then also be shrunk and searched for data a lot faster. Different hash functions come with different advantages and drawbacks which makes some of them better suited for a specific application than others. The purpose of this seminar topic is to give an overview over different hash algorithms applied to data mapping tasks, their advantages and drawbacks.

Beyond the single-core era, Moore's Law was achieved by combining several processing units to multicore systems - be it in a homogenous or heterogeneous fashion. However, with increasing number of processing untis, these architectures face scalability issues. Thus, the arising trend towards distributed or tile-based architectures seems to be a beneficial solution to satisfy the growing demand oof processing power.

However, the shift towards distributed architectures often implies also a distributed memory hierarchy in order to avoid access hotspots. This arises potential data-to-task dislocalities, often referred to as "locality wall". Several trends, such as data-migration, task-migration or near-memory computing promise to increase data-to-task locality and to reduce the data traffic within the system - nowadays the most prominent energy sink in computer architectures.

The task during the seminar consists of an exhausitve literature study on that topic in order to describe, analyze and compare the most important approaches.

o.lenke@tum.de

tim.twardzik@tum.de

A survey paper on application profiling tools in Linux.

Lars Nolte

lars.nolte@tum.de

A survey paper on inter-process communication mechanisms.

Lars Nolte

lars.nolte@tum.de

Multiobjective Genetic algorithms (MOGA) is a well-known optimization approach for many real-world problems including embedded systems design. The MOGA results in the formation of a Pareto optimal set that allows the designer to choose points based on his desired tradeoff between the objectives. One of the computationally expensive parts of MOGA is a nondominated sorting of the solutions. It has a significant impact on the quality of population and selection of individuals from the population for the genetic operation as well as Pareto set formation. There has been a significant amount of research on nondominated sorting and selection approaches over the past decades.

This seminar aims to summarize the multiple variants of the Nondominated Sorting Genetic Algorithm (NSGA) and identify the benefits and drawbacks on real-world MOGA applications.

Manu Manuel

manu.manuel@tum.de

Processing-in-memory (PIM) and Near-memory Computing are promising strategies to tackle the major limitations of today's system's growth, such as power consumption and data traffic by inreasing the performance simultaneously. However, these appraoches require typically an enormous development effort and pre-estimating the benefits qunatitatively is difficult.

The task during the seminar consists of an exhausitve literature study on that topic in order to describe, analyze and compare the most important approaches.

o.lenke@tum.de