With the advances in IC fabrication technology and high integration density of transistors per chip area, it would be possible to design multicore chips with thousands of processing elements by 2025. To harness the benefits of invasive computing we propose a scalable approach of coupling standard IP based MPSoCs over an invasive network on chip ( iNoC) to build a many core platform.
In this sub-project we strive to enable MPSoC platforms consisting of loosely-coupled standard RISC processors for performance-optimized and energy-efficient invasive computing. The major research focus is on
- functional extensions on the hardware level to optimize latency and software overhead when distributing application threads among processing elements (Cores).
- extensions for providing a low power infrastructure designed for the resource-aware application paradigm of invasive computing.
The central idea of invasive computing is resource aware programming. Applications dynamically decide which resources to use (infect) and expand and/or shrink on demand depending on their thread (ilet) level parallelism and resource availability. Our approach is to build in-hardware support for
- Resource awareness and
- Assistance for infections or ilet binding
by having special hardware enhancements called Core ilet Controllers (CiC).
The idea is to perform a hardware-software co-optimized functional partitioning, and delegate those functions to CiCs that can be implemented with much lower latency and power dissipation in hardware.
Offloading latency-critical tasks from software to dedicated hardware modules as well as dynamic utilization management of individual cores contribute to increased power efficiency of the invasive many-core SoC. As well such a hardware enhancement provides as a means of implementing a scalable decentralized ilet mapping policy taking into account the local up-to-date cores utilization and other hardware resource status information.
In subproject B3 we are working in close cooperation with Chair for Embedded Systems, KIT.
Dark silicon management: an integrated and coordinated cross-layer approach. it - Information Technology 58 (6), 2016, 297–307 mehr… BibTeX Volltext ( DOI )
TCU: A Multi-Objective Hardware Thread Mapping Unit for HPC Clusters. International Supercomputing Conference High Performance -- ISC 2016, 2016 mehr… BibTeX
DiaSys: On-Chip Trace Analysis for Multi-processor System-on-Chip. Architecture of Computing Systems -- ARCS 2016 (Springer Lecture Notes 9637), Springer International Publishing, 2016, 197-209 mehr… BibTeX Volltext ( DOI ) Volltext (mediaTUM)
Knowledge-Based On-Chip Diagnosis for Multi-Core Systems-on-Chip. edaWorkshop 15, 2015, 39-45 mehr… BibTeX Volltext (mediaTUM)
A Hardware-based Multi-objective Thread Mapper for Tiled Manycore Architectures. 33rd IEEE International Conference on Computer Design (ICCD), 2015 mehr… BibTeX Volltext ( DOI )
Potentials and Challenges for Multi-Core Processors in Robotic Applications. Workshop "Roboterkontrollarchitekturen" auf der Informatik 2013, 43. Jahrestagung der Gesellschaft für Informatik, GI-Edition "Lecture Notes in Informatics" (LNI), 2013 mehr… BibTeX
Invasive Manycore Architectures. Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), 2012 mehr… BibTeX
Hardware Assisted Thread Assignment for RISC based MPSoCs in Invasive Computing. International Symposium on Integrated Circuits (ISIC), 2011 mehr… BibTeX