InvasIC B5 - Invasive NoCs – Autonomous, Self-Optimising Communication Infrastructures for MPSoCs

Networks-on Chip (NoC) have emerged for providing scalable on-chip communication interconnects and better modularity than the global
bus based systems. Early research in NoC architectures was conducted towards the goal to provide an optimized topology in terms of throughput, latency and area for a given application.

In the scope of invasive computing, the sub-project InvasIC-B5 studies novel NoC concepts to provide performance improvments for a wide range of applications. NoC architecture supporting these concepts are called invasive NoCs or iNoCs. In addition to standard packet routing, an iNoC shall support the invasion of application-specific routing channels and topologies during the lifetime of an application. This will help to provide guaranteed bandwidth to such applications by ensuring the optimized link utilization of on-chip communication infrastructure.

Research dimensions

Motivation behind this sub-project is to investigate and design invasible Networks-on-Chip, iNoCs with emphasis on three major research areas.

  • Novel router functions and protocols for invasion of communication channels
  • Detailed link characterisation and prediction through run-time monitoring for improving communication and resource utilisation by means of self-adaptation
  • De-centralized algorithms and strategies for low cost and low latency embedding of application-specific communication patterns

iNA-Invasive Network Adapter

Invasive Network Adapter (iNA) is an interface unit between resources contained in loosely coupled MPSoC compute tiles and the iNoC router. In contrast to network adapters for conventional NoCs, the InvasIC NA supports separate channels for processing data and invasion control.

iNA supports differentiated service channels (QoS) for different traffic types between the intra-tile bus interconnect and the iNoC router. In addition, the exchange of invasive computing specific data/commands to CIC (sub-project B3) are facilitated through a separate control channel . Invasive NA also enables the iNoC router to access the iRTSS and agent middleware software services (sub-project C1)  running on the compute tiles.


  • 1/17
    Akshay Srivatsa, Sven Rheindt, Dirk Gabriel, Thomas Wild, Andreas Herkersdorf: CoD: Coherence-on-Demand – Runtime Adaptable Working Set Coherence for DSM-based Manycore Architectures. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIX) , 2019 mehr… BibTeX
  • 2/17
    Sven Rheindt, Sebastian Maier, Florian Schmaus, Thomas Wild, Wolfgang Schröder-Preikschat, Andreas Herkersdorf: SHARQ: Software-Defined Hardware-Managed Queues for Tile-Based Manycore Architectures. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIX), 2019 mehr… BibTeX
  • 3/17
    Sven Rheindt, Andreas Fried, Oliver Lenke, Lars Nolte, Thomas Wild, Andreas Herkersdorf: NEMESYS: Near-Memory Graph Copy Enhanced System-Software. MEMSYS 19: The International Symposium on Memory Systems, 2019 mehr… BibTeX
  • 4/17
    Sven Rheindt, Andreas Schenk, Akshay Srivatsa, Thomas Wild and Andreas Herkersdorf: CaCAO: Complex and Compositional Atomic Operations for NoC-based Manycore Platforms. ARCS 2018 - 31st International Conference on Architecture of Computing Systems, 2018 mehr… BibTeX
  • 5/17
    Leonard Masing, Akshay Srivatsa, Fabian Kress, Nidhi Anantharajaiah, Andreas Herkersdorf, Juergen Becker: In-NoC-circuits for low-latency cache coherence in distributed shared-memory architectures. 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018 mehr… BibTeX
  • 6/17
    Akshay Srivatsa, Sven Rheindt, Thomas Wild, Andreas Herkersdorf: Region Based Cache Coherence for Tiled MPSoCs. 2017 30th IEEE International System-on-Chip Conference (SOCC), 2017 mehr… BibTeX
  • 7/17
    Preethi Parayil Mana Damodaran, Aurang Zaib, Thomas Wild, Stefan Wallentowitz, Andreas Herkersdorf: Sharer Status-based Caching in tiled Multiprocessor Systems-on-Chip. HPC 2015, 2015 mehr… BibTeX
  • 8/17
    Andreas Weichslgartner, Jan Heisswolf, Aurang Zaib, Thomas Wild, Andreas Herkersdorf, Jürgen Becker and Jürgen Teich: Position Paper: Towards Hardware-Assisted Decentralized Mapping of Applications for Heterogeneous NoC Architectures. Second International Workshop on Multi-objective Many-core design (MOMAC), 2015 mehr… BibTeX
  • 9/17
    Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf: Network Interface with Task Spawning Support for NoC-Based DSM Architectures. Architecture of Computing Systems--ARCS 2015, 2015 mehr… BibTeX
  • 10/17
    Jan Heisswolf, Aurang Zaib, Andreas Zwinkau, Sebastian Kobbe, Andreas Weichslgartner, Jürgen Teich, Jörg Henkel, Gregor Snelting, Andreas Herkersdorf, Jürgen Becker: CAP: Communication Aware Programming. Design Automation Conference (DAC), 51th ACM / EDAC / IEEE, 2014 mehr… BibTeX
  • 11/17
    Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Martin Karle, Maximilian Singh, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker: The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure. Proceedings of the first International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS), 2014 mehr… BibTeX
  • 12/17
    J. Heisswolf, A. Zaib, A. Weichslgartner, R. König, T. Wild, A. Herkersdorf, J. Teich and J. Becker: Virtual Networks - Distributed Communication Resource Management. In: Transactions on Reconfigurable Technology and Systems (TRETS). ACM, 2013 mehr… BibTeX
  • 13/17
    Andreas Herkersdorf, Johny Paul, Ravi Kumar Pujari, Walter Stechele, Stefan Wallentowitz, Thomas Wild, Aurang Zaib: Potentials and Challenges for Multi-Core Processors in Robotic Applications. Workshop "Roboterkontrollarchitekturen" auf der Informatik 2013, 43. Jahrestagung der Gesellschaft für Informatik, GI-Edition "Lecture Notes in Informatics" (LNI), 2013 mehr… BibTeX
  • 14/17
    Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf: AUTO-GS: Self-optimization of NoC Traffic Through Hardware Managed Virtual Connections. 16th EUROMICRO Digital System Design (DSD) Conference, 2013 mehr… BibTeX
  • 15/17
    Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Ralf König, Thomas Wild, Andreas Herkersdorf, Jürgen Teich, Jürgen Becker: Hardware Supported Adaptive Data Collection for Networks on Chip. IPDPS PhD Forum - 27th IEEE International Symposium on Parallel & Distributed Processing, 2013 mehr… BibTeX
  • 16/17
    Jörg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hübner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, Sebastian Kobbe: Invasive Manycore Architectures. Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), 2012 mehr… BibTeX
  • 17/17
    Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf Koenig, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker: Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS. IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum (IPDPSW), 2012 mehr… BibTeX