Networks-on Chip (NoC) have emerged for providing scalable on-chip communication interconnects and better modularity than the global
bus based systems. Early research in NoC architectures was conducted towards the goal to provide an optimized topology in terms of throughput, latency and area for a given application.
In the scope of invasive computing, the sub-project InvasIC-B5 studies novel NoC concepts to provide performance improvments for a wide range of applications. NoC architecture supporting these concepts are called invasive NoCs or iNoCs. In addition to standard packet routing, an iNoC shall support the invasion of application-specific routing channels and topologies during the lifetime of an application. This will help to provide guaranteed bandwidth to such applications by ensuring the optimized link utilization of on-chip communication infrastructure.
Motivation behind this sub-project is to investigate and design invasible Networks-on-Chip, iNoCs with emphasis on three major research areas.
- Novel router functions and protocols for invasion of communication channels
- Detailed link characterisation and prediction through run-time monitoring for improving communication and resource utilisation by means of self-adaptation
- De-centralized algorithms and strategies for low cost and low latency embedding of application-specific communication patterns
Invasive Network Adapter (iNA) is an interface unit between resources contained in loosely coupled MPSoC compute tiles and the iNoC router. In contrast to network adapters for conventional NoCs, the InvasIC NA supports separate channels for processing data and invasion control.
iNA supports differentiated service channels (QoS) for different traffic types between the intra-tile bus interconnect and the iNoC router. In addition, the exchange of invasive computing specific data/commands to CIC (sub-project B3) are facilitated through a separate control channel . Invasive NA also enables the iNoC router to access the iRTSS and agent middleware software services (sub-project C1) running on the compute tiles.
CoD: Coherence-on-Demand – Runtime Adaptable Working Set Coherence for DSM-based Manycore Architectures. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIX) , 2019 mehr… BibTeX
SHARQ: Software-Defined Hardware-Managed Queues for Tile-Based Manycore Architectures. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIX), 2019 mehr… BibTeX
NEMESYS: Near-Memory Graph Copy Enhanced System-Software. MEMSYS 19: The International Symposium on Memory Systems, 2019 mehr… BibTeX
CaCAO: Complex and Compositional Atomic Operations for NoC-based Manycore Platforms. ARCS 2018 - 31st International Conference on Architecture of Computing Systems, 2018 mehr… BibTeX
In-NoC-circuits for low-latency cache coherence in distributed shared-memory architectures. 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018 mehr… BibTeX
Region Based Cache Coherence for Tiled MPSoCs. 2017 30th IEEE International System-on-Chip Conference (SOCC), 2017 mehr… BibTeX
Sharer Status-based Caching in tiled Multiprocessor Systems-on-Chip. HPC 2015, 2015 mehr… BibTeX
Position Paper: Towards Hardware-Assisted Decentralized Mapping of Applications for Heterogeneous NoC Architectures. Second International Workshop on Multi-objective Many-core design (MOMAC), 2015 mehr… BibTeX
Network Interface with Task Spawning Support for NoC-Based DSM Architectures. Architecture of Computing Systems--ARCS 2015, 2015 mehr… BibTeX
CAP: Communication Aware Programming. Design Automation Conference (DAC), 51th ACM / EDAC / IEEE, 2014 mehr… BibTeX
The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure. Proceedings of the first International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS), 2014 mehr… BibTeX
Virtual Networks - Distributed Communication Resource Management. In: Transactions on Reconfigurable Technology and Systems (TRETS). ACM, 2013 mehr… BibTeX
Potentials and Challenges for Multi-Core Processors in Robotic Applications. Workshop "Roboterkontrollarchitekturen" auf der Informatik 2013, 43. Jahrestagung der Gesellschaft für Informatik, GI-Edition "Lecture Notes in Informatics" (LNI), 2013 mehr… BibTeX
AUTO-GS: Self-optimization of NoC Traffic Through Hardware Managed Virtual Connections. 16th EUROMICRO Digital System Design (DSD) Conference, 2013 mehr… BibTeX
Hardware Supported Adaptive Data Collection for Networks on Chip. IPDPS PhD Forum - 27th IEEE International Symposium on Parallel & Distributed Processing, 2013 mehr… BibTeX
Invasive Manycore Architectures. Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), 2012 mehr… BibTeX
Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS. IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum (IPDPSW), 2012 mehr… BibTeX