InvasIC Z2 - Validation and Demonstrator

Motivation and Targets

Subproject Z2 describes the FPGA-based demonstrator platform which will be required a) for early evaluation of invasive hardware, software, and algorithmic concepts, b) reduction of design risks for subsequent ASIC design and development, and c) for prototyping a complete heterogeneous invasive MPSoC as simulation-based approaches alone will not able to cope with this enormous complexity or be not accurate enough.

FPGA based Prototyping

For demonstration and verification of our invasive computing platform we are using a FPGA based prototyping system. The "CHIPit" system consist of six high-end virtex-5 FPGAs, each one offering of more than 50000 slices. The size of one FPGA is large enough to hold about 10 processing cores (CPUs). Each FPGA is connected to 8 MB of SSRAM, furthermore the system is equipped with two DDR2 extension board providing additional 512 MB of memory. The 6 FPGA are connected to each other via switchable routes, which allows for a very flexible interconnection.    


Another main benefit of the CHIPit system is its comprehensive simulation and debugging ability. The system offers a proprietary connection to a host PC, called Universal Multi-Resource (UMR) Bus. This UMR bus has several functions. On the one hand it used to upload the bitstreams onto the FPGAs and configure the switchable routes and clock generators. On the other hand it can be used as a high-speed debug connector for co-simulation or transaction based verification. For instance, one can run the DUT in Hardware on the CHIPit system while the Testbench connected to the DUT is running on a host PC which allows for very fast simulation of Hardware, as complex parts are running in HW.  This approach makes it possible for us to test parts of our invasive computing platform isolated from, e.g. not finished parts, in an early stage of the project on real hardware.


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    Stephanie Friederich, Jan Heisswolf, David May, Jürgen Becker: Hardware prototyping and software debugging of multi-core architectures. Synopsys User Group Meeting (SNUG), 2014 mehr… BibTeX
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    Jürgen Becker, Stephanie Friederich, Jan Heisswolf, Ralf Koenig, David May: Hardware Prototyping of Novel Invasive Multicore Architectures. Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), 2012 mehr… BibTeX