Akshay Srivatsa, M.Sc.

Wissenschaftlicher Mitarbeiter

Technische Universität München
Fakultät für Elektrotechnik und Informationstechnik
Lehrstuhl für Integrierte Systeme
Arcisstr. 21
80290 München

Tel.: +49.89.289.22963
Fax: +49.89.289.28323
Gebäude: N1 (Theresienstr. 90)
Raum: N2140
Email: srivatsa.akshay@tum.de

Lehre

Project Laboratory IC Design (WS 2018-19, SS 2021)

System-on-Chip Platforms (Since SS 2016)

Angebotene Arbeiten

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Betreute Arbeiten

  • Emulating Dynamic Frequency-Scaling (DFS) for the LEON3 Processor on an FPGA Prototype
    (Master Thesis, Li-Yu Peng, 2021)
  • Adapting Coherency Mechanisms to Execute Shared Memory Workloads on a DSM-based Manycore Architecture
    (Master Thesis, Mostafa Mansour, 2021)
  • Integrating and Optimizing a Hybrid Voting-based Eviction Policy for Manycore Architectures on an FPGA Prototype
    (Master Thesis, Miguel Montoya Rendon, 2020)
  • Exploring the Feasibility and Benefit of Integrating a Learning-based Policy into HyVE
    (Research Internship, Eslam Hussein, 2020)
  • Implementing a Hybrid Voting-based Eviction Policy on a FPGA Prototype
    (Working Student, Eslam Hussein, 2020)
  • Exploring a Hybrid Voting-based Eviction Policy for Last Level Caches
    (Master Thesis, Sebastian Nagel, 2020) VDE Bayern Award 2020
  • Exploring a Hybrid Cache Eviction Policy using Gem5
    (Research Internship, Leonardo Davinci Darwin, 2020)
  • Design and Implementation of a Coherence-Barrier for RBCC on an FPGA Prototype
    ( Research Internship, Mostafa Mansour, 2020)
  • A Hardware Mechanism with Detect and Resolve False- Sharing for Region-Based Cache Coherence
    (Research Internship, Li-Yu Peng, 2020)
  • Extension of RBCC to DDR and Evaluation of Sparse Directory Eviction Policies
    (Research Internship, Miguel Montoya Rendon, 2019)
  • Runtime Re-configuration of Region-Based Cache Coherence for DSM-based MPSoCs
    (Master Thesis, Sai Varun Brahmadevara, 2019)
  • High Level Simulation of a Smart Eviction Policy for Caches
    (Research Internship, Stephen Bullock, 2019)
  • A Hardware Mechanism to Detect & Resolve False-Sharing for Region-based Cache Coherence
    (Research Internship, Mohamed Gaith, 2019)
  • Compact Directories with Hybrid Architecture Aware Eviction Policies for Distributed Shared Memory MPSoCs
    (Master Thesis, Nael Fasfous, 2018) VDE Bayern Award 2019
  • Optimizing Cache Coherence for MPSoCs with Distributed Shared Memories using a High Level Simulation Model
    (Master Thesis, Yifang Wang, 2018)
  • Accelerated Cache Coherence for the InvasIC Architecture
    (Research Internship, Yifang Wang, 2016)
  • High Level Modelling of the InvasIC Architecture using Gem5
    (Working Student, Mengyu Liang, 2016)

Publikationen

  • Akshay Srivatsa, Nael Fasfous, Nguyen Anh Vu Doan, Sebastian Nagel, Thomas Wild, Andreas Herkersdorf: Exploring a Hybrid Voting-based Eviction Policy for Caches and Sparse Directories on Manycore Architectures. Microprocessors and Microsystems, 2021 mehr… BibTeX
  • Sven Rheindt, Akshay Srivatsa, Oliver Lenke, Lars Nolte, Thomas Wild, Andreas Herkersdorf: Tackling the MPSoC Data Locality Challenge – Part 2 / Chapter 5. In: Multi-Processor System-on-Chip 1. Wiley Online Library, 2021, 87-114 mehr… BibTeX
  • Akshay Srivatsa, Mostafa Mansour, Sven Rheindt, Dirk Gabriel, Thomas Wild, Andreas Herkersdorf: DynaCo: Dynamic Coherence Management for Tiled Manycore Architectures. International Journal of Parallel Programming, 2020 mehr… BibTeX
  • Akshay Srivatsa, Sebastian Nagel, Nael Fasfous, Doan Nguyen Anh Vu, Thomas Wild, Andreas Herkersdorf: HyVE: A Hybrid Voting-based Eviction Policy for Caches. IEEE Nordic Circuits and Systems Conference (NorCAS 2020), 2020 mehr… BibTeX
  • Nguyen Anh Vu Doan, Akshay Srivatsa, Nael Fasfous, Sebastian Nagel, Thomas Wild, Andreas Herkersdorf: On-Chip Democracy: A Study on the Use of Voting Systems for Computer Cache Memory Management. International Conference on Industrial Engineering and Engineering Management (IEEM), 2020 mehr… BibTeX
  • Akshay Srivatsa, Sven Rheindt, Dirk Gabriel, Thomas Wild, Andreas Herkersdorf: CoD: Coherence-on-Demand - Runtime Adaptable Working Set Coherence for DSM-based Manycore Architectures. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIX) , 2019 mehr… BibTeX
  • Sven Rheindt, Andreas Schenk, Akshay Srivatsa, Thomas Wild, Andreas Herkersdorf: CaCAO: Complex and Compositional Atomic Operations for NoC-based Manycore Platforms. ARCS 2018 - 31st International Conference on Architecture of Computing Systems, 2018 mehr… BibTeX
  • Leonard Masing, Akshay Srivatsa, Fabian Kress, Nidhi Anantharajaiah, Andreas Herkersdorf, Juergen Becker: In-NoC-circuits for low-latency cache coherence in distributed shared-memory architectures. 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018 mehr… BibTeX
  • Akshay Srivatsa, Sven Rheindt, Thomas Wild, Andreas Herkersdorf: Region Based Cache Coherence for Tiled MPSoCs. 2017 30th IEEE International System-on-Chip Conference (SOCC), 2017 mehr… BibTeX