Akshay Srivatsa, M.Sc.

Wissenschaftlicher Mitarbeiter  

Technische Universität München
Fakultät für Elektrotechnik und Informationstechnik
Lehrstuhl für Integrierte Systeme
Arcisstr. 21
80290 München

Tel.: +49.89.289.22963
Fax: +49.89.289.28323
Gebäude: N1 (Theresienstr. 90)
Raum: N2140
Email: srivatsa.akshay@tum.de

Lehre

Project Laboratory IC Design (WS 2018-19)

System-on-Chip Platforms (Since SS 2016)

Angebotene Arbeiten

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Laufende Arbeiten

Masterarbeiten

Exploring the Dynamicity of Region Based Cache Coherence for Distributed Shared Memory MPSoCs on an FPGA Prototype

Forschungspraxis (Research Internship)

Exploring Alternative Coherence Protocols for Region-based Cache Coherence on an FPGA Prototype

False-Sharing Resolution: A Hardware Mechanism to Detect & Resolve False-Sharing for Region Based Cache Coherence

Extending Region Based Cache Coherence to Global (DDR) Memory for Distributed Shared MPSoCs on an FPGA Prototype

Implementing Smart Eviction Policies for Directories in Gem5

Seminare

A Survey on Replacement Policies for Caches/Directories

A Survey on Replacement Policies for Caches/Directories

Betreute Arbeiten

  • A Hardware Mechanism to Detect & Resolve False-Sharing for Region-based Cache Coherence (Research Internship, Mohamed Gaith, 2019)
  • Compact Directories with Hybrid Architecture Aware Eviction Policies for Distributed Shared Memory MPSoCs (Master Thesis, Nael Fasfous, 2018)
  • Optimizing Cache Coherence for MPSoCs with Distributed Shared Memories using a High Level Simulation Model (Master Thesis, Yifang Wang, 2018)
  • Accelerated Cache Coherence for the InvasIC Architecture
    (Research Internship, Yifang Wang, 2016)
  • High Level Modelling of the InvasIC Architecture using Gem5
    (Working Student, Mengyu Liang, 2016)
  • High Level Simulation of a Smart Eviction Policy for Caches
    (Research Internship, Stephen Bullock, 2019)

Publikationen

  • Akshay Srivatsa, Sven Rheindt, Dirk Gabriel, Thomas Wild, Andreas Herkersdorf: CoD: Coherence-on-Demand – Runtime Adaptable Working Set Coherence for DSM-based Manycore Architectures. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIX) , 2019 more… BibTeX
  • Sven Rheindt, Andreas Schenk, Akshay Srivatsa, Thomas Wild and Andreas Herkersdorf: CaCAO: Complex and Compositional Atomic Operations for NoC-based Manycore Platforms. ARCS 2018 - 31st International Conference on Architecture of Computing Systems, 2018 more… BibTeX
  • Leonard Masing, Akshay Srivatsa, Fabian Kress, Nidhi Anantharajaiah, Andreas Herkersdorf, Juergen Becker: In-NoC-circuits for low-latency cache coherence in distributed shared-memory architectures. 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018 more… BibTeX
  • Akshay Srivatsa, Sven Rheindt, Thomas Wild, Andreas Herkersdorf: Region Based Cache Coherence for Tiled MPSoCs. 2017 30th IEEE International System-on-Chip Conference (SOCC), 2017 more… BibTeX