Tracing of thread execution and memory allocation

5G ultra-reliable low-latency communications

Dynamic ROI size adaptation to increase frame rates of high speed 3D laser line scanners (at SmartRay GmbH in Wolfratshausen)

Development of a Concept to Enable Access to Heavily Shared Resources in an MPSoC Featuring a Hybrid NoC

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Exploring the Dynamicity of Region Based Cache Coherence for Distributed Shared Memory MPSoCs on an FPGA Prototype

Design and Implementation of a Network Interface for a Fault-Tolerant Hybrid Network on Chip

Interference Channel Analysis (at GE Aviation)