Offene Arbeiten


Tracing of thread execution and memory allocation

5G ultra-reliable low-latency communications

Laufende Arbeiten


Evaluating Shared Memory Workloads on a DSM-based MPSoC using Region Based Cache Coherence

Exploring Hybrid Replacement Policies for Caches on an FPGA Prototype

Efficient Instruction Set Architecture for Convolutional Neural Network Accelerators

Flexible On-Chip Networks for Convolutional Neural Network Accelerators

Power Modeling on FPGA for Approximate Computing

Design and Implementation of a DMA Controller in a Network Interface for a Fault-Tolerant Hybrid Network on Chip

FPGA-Based Cell Detection for Digital Holographic Microscopy