Brederlow, Ralf


Foto von Ralf Brederlow

Prof. Dr.-Ing. Ralf Brederlow

Technische Universität München

Lehrstuhl für Schaltungsentwurf (Prof. Brederlow)

  • Tel.: +49 (89) 289 - 22922
  • Sprechstunde: nach Vereinbarung (bitte Fr. Artinger kontaktieren)
  • Raum: 0103.05.315

Wissenschaftliche Laufbahn und Forschungsgebiete

Prof. Ralf Brederlow‘s (*1970) Forschungsgebiet ist die integrierte CMOS Schaltungstechnik und die intelligente Sensorik – d.h. Sensoranwendungen im Internet der Dinge, bei denen eine Vielzahl von Sensoren mit Hilfe kleinster analoger und digitaler mikroelektronischer Schaltungen zu einem wesentlich genaueren und flexibleren Sensorsystem zusammengefasst werden.

Ralf Brederlow studierte Physik an der Universität Würzburg und der TU München. Danach promovierte bei der Zentralen Forschung der Siemens AG und der TU Berlin in Elektrotechnik. Seit 1999 arbeitete er bei Infineon an analogen, mikroelektronischen Schaltungs- und Technologiekonzepten. Seit 2006 war er Gruppen- und später Entwicklungsleiter bei Texas Instruments. Hier betreute er die Schaltungs- und Technologieentwicklung für eine auf niedrigsten Energieverbrauch optimierte Mikrocontroller Produktfamilie (MSP430). 2015 war er federführend am Aufbau einer Forschungsabteilung (Kilby Labs) in Freising beteiligt und beschäftigte sich dort bis 2019 mit intelligenten Sensoren und Kommunikationsschaltungen mit kurzer Reichweite.

 

Publication (Journals)

[23]

 

[22]

U.Nurmetov, T.Fritz, E.Muellner, CM.Dougherty, M.Szelong, F.Kreupl, R.Brederlow, ´A CMOS-Temperature Stabilized 2 Dimensional Mechanical Stress Sensor with 11 bit Resolution`IEE Journal of Solid State Circuits, 2020,

F. Santoro, R. Kuhn, N. Gibson, N. Rasera, T. Tost, H. Graeb, B. Wicht, and R. Brederlow ‘A Hysteretic Buck Converter with 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications’ , IEEE Journal of Solid State Circuits, Vol. 53(8), pp. 1856-1868

[21] M. Lüders, B. Eversmann, J. Gerber, K. Huber, R. Kuhn, D. Schmitt-Landsiedel, and R. Brederlow‚ ‘Architectural and Circuit Design Techniques for Power Management of Ultra-Low-Power MCU Systems’, IEEE Transactions on VLSI Systems Vol. (99), 2013, pp. 1-10
[20] V. Ivanov, R. Brederlow, and J. Gerber, ‘An ultra-low power bandgap operational at supply as low as 0.75V’, IEEE Journal of Solid State-Circuits, Vol. 47 (7), 2012, pp. 1515-23
[19] J. Koh, R. Thewes, D. Schmitt-Landsiedel, and R. Brederlow, ‘A Complementary Switched MOSFET Architecture for the 1/f Noise Reduction in Linear Analog CMOS IC’s’, IEEE Journal of Solid-State Circuits, vol. 42 (6), 2007, pp. 1352-1361
[18] G. I. Wirth, R. da Silva, and R. Brederlow, ’Statistical Model for the Circuit Bandwidth Dependence of Low-Frequency Noise in Deep-Submicrometer MOSFETs’, IEEE Transactions on Electron Devices, vol. 54 (2), 2007, pp. 340-345
[17] R. Brederlow, J. Koh, and R. Thewes, ‘A physics-based low frequency noise model for MOSFETs under periodic large signal excitation’, (invited), Journal of Solid-State Electronics 50, 2006, pp. 668-673
[16] R. da Silva, G. I. Wirth, and R. Brederlow, ‘Novel analytical and numerical approach to model low frequency noise in semiconductor devices’, Physica A 362, 2006, pp. 277-288
[15] G. I. Wirth, R. da Silva, J. Koh, R. Thewes, and R. Brederlow, ‘Modeling of Statistical Low-Frequency Noise of Deep-Submicron MOSFETs’, IEEE Transactions on Electron Devices, Vol.52, N° 7, 2005, pp. 1576-1588
[14] K. von Arnim, E. Borinski, P. Seegebrecht, H. Fiedler, R. Brederlow, R. Thewes, J. Berthold, and Ch. Pacha, ‘Efficiency of Body Biasing in 90 nm CMOS for Low Power Digital Circuits’, Journal of Solid-State Electronics, Vol.40, N° 7, 2005, pp. 1549-1556
[13] H. S. Bennett, R. Brederlow, P. Cottrell, J. Costa, M. Huang, A. A. Immorlica Jr., J.-E. Mueller, M. Racanelli, S. Shichijo, Ch. Weitzel, and B. Zhao, ‘Device and Technology Evolution for Si-Based RF Integrated Circuits’, IEEE Transactions on Electron Devices, Vol.52, N°.7, 2005, pp.1235-1258
[12] Ch. Schlünder, R. Brederlow, B. Ankele, W. Gustin, K. Goser, and R. Thewes, ‘Effects of inhomogenous negative bias temperature stress on p-channel MOSFETs of anolog and RF circuits’, Journal on Microelectronics Reliability, Vol. 45, 2005, pp. 39-46
[11] H. S. Bennett, R. Brederlow, J. Costa, M. Huang, A. A. Immorlica Jr., J.-E. Mueller, M. Racanelli, Ch. Weitzel, and B. Zhao, ‘Circuits and Devices for Wireless Communications’ (invited), IEEE Circuits and Devices Magazine, Nov/Dec 2004, pp. 39-51
[10] R. Thewes, F. Hofmann, A. Frey, M. Schienle, C. Paulus, P. Schindler-Bauer, B. Holzapfl, and R. Brederlow, ‘CMOS-based DNA Sensor Arrays’, in ‘Advanced Micro and Nano Systems – Enabling Technology for MEMS and Nanodevices’, H. Baltes, O. Brand, G. Fedder, C, Hierold, J. Korvink, O. Tabata, ed., Wiley-VCH, 2004
[9] B. Eversmann, M. Jenkner, Ch. Paulus, R. Brederlow, F. Hofmann, B. Holzapfl, R. Thewes, P. Fromherz, R. Gabl, G. Eckstein, and D. Schmitt-Landsiedel, ‘A 128 x 128 CMOS Sensor Array for Monitoring Neural Signals of Living Cells’, IEEE Journal of Solid State Circuits, 2003, Vol. 38, N° 12, pp. 2306-2317
[8] R. Brederlow, W. Weber, D. Schmitt-Landsiedel, and R. Thewes, ‘Hot-carrier degradation of the low-frequency noise in MOS transistors under analog and RF operating conditions’, IEEE Transactions on Electron Devices, Vol. 49, N°9, 2002, pp. 1588-1596
[7] R. Brederlow, W. Weber, S. Donnay, P. Wambacq, J. Sauerer, and M. Vertregt, ‘A Mixed-Signal Roadmap for the International Technology Roadmap for Semiconductors‘, IEEE Journal on Design and Test for Computers, Vol. 18, N°6, 2001, pp. 34-46
[6] R. Brederlow, W. Weber, C. Dahl, D. Schmitt-Landsiedel, and R. Thewes, ‘Low-Frequency Noise of Integrated Poly-Silicon Resistors’, IEEE Transactions on Electron Devices 48 (6), 2001, pp. 1180-1187
[5] R. Thewes, C. Linnenbank, U. Kollmer, S. Burges, M. DiLeo, M. Clinchy, U. Schaper, R. Brederlow, R. Seibert, and W. Weber, ‘On the Matching Behavior of MOSFET Small Signal Parameters’, IEEE El. Dev. Lett. 21 (12), 2000, pp. 552-553
[4] R. Thewes, R. Brederlow, Ch. Schlünder, P. Wieczorek, B. Ankele, A. Hesener, J. Holz, S. Kessel, and W. Weber, ‘MOS Transistor Reliability under Analog Operation’ (invited), Journal on Microelectronics Reliability 40, 2000, pp. 1545-1554
[3] A. Luck, S. Jung, R. Brederlow, R. Thewes, K. Goser, and W. Weber, 'On the Design Robustness of Threshold Logic Gates Using Multi Input Floating Gate MOS Transistors', IEEE Transactions on Electron Devices 47 (6), 2000, pp. 1231-1240
[2] Ch. Schlünder, R. Brederlow, P. Wieczorek, C. Dahl, J. Holz, M. Röhner, S. Kessel, V. Herold, K. Goser, W. Weber, and R. Thewes, 'Trapping Mechanisms in Negative Bias Temperature Stressed p-MOSFETs ', Microelectronics Reliability 39, 1999, pp. 821-826
[1] G. Walter, W. Weber, R. Brederlow, R. Jurk, C. Linnenbank, D. Schmitt-Landsiedel, and R. Thewes, ‘Precise quantitative evaluation of the hot-carrier induced drain series resistance degradation in LATID n-MOSFETs‘, Journal on Microelectronics Reliability. 38, 1998, pp. 1063-1068

Publications (Conferences)

[46]     MOCAS

[45]     NEWCAS

[44]     J. Nurmetov, T. Fritz, E. Muellner, C. Dougherty, F. Kreupl, and R. Brederlow CMOS Temperature Stabilized 2-Dimensional Mechanical Stress Sensor with 11-bit Resolution, Very Large Scale Integrated Circuits Symposium VLSI, pp. 64-65, 2019

[43]   F. Santoro, R. Kuhn, N. Gibson, N. Rasera, T. Tost, D. Schmitt-Landsiedel and R. Brederlow, ‘A 92.1% Efficient DC-DC Converter for Ultra-Low Power Microcontrollers with Fast Wake-up’, Proceedings of the Custom Integrated Circuit Conference, 2017, pp.

[42]     O.M. Guillen, F. De Santis, R. Brederlow, G. Sigl, ‘Towards Side-Channel Secure Firmware Updates’, Cuppens F., Wang L., Cuppens-Boulahia N., Tawbi N., Garcia-Alfaro J. (eds) Foundations and Practice of Security (FPS) 2016, Lecture Notes in Computer Science, vol. 10128 Springer, Cham

[41]     F. Santoro, N. Gibson, R. Kuhn, T. Tost, D. Schmitt-Landsiedel and R. Brederlow, ‘An ultra-low power, 2mA Iout buck converter optimized for <50mV ripple at a load cap of only 27nF’, Proceedings of the 11th IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME), 2015, pp. 208-11

[40]     O. M. Guillen, R. Brederlow, R. Ledwa, and G. Sigl, ‘Risk management in embedded devices using metering applications as example’, Proceedings of the 9th Workshop on Embedded Systems Security 14, 2014, pp. 6:1-9

[39]     A. Baumann, M. Jung, K. Huber, M. Arnold, C. Sichert, S. Schauer and R. Brederlow, ‘A MCU platform with embedded FRAM achieving 350nA current consumption in real-time clock mode with full state retention and 6.5µs system wakeup time’, Proceedings of Very Large Scale Integrated Circuits Symposium VLSI 2013, pp. 202-203

[38]     R. Brederlow, ‘The human factor in mixed-signal design and its consequences for design and automation,’ Technical Digest 27th Symposium on Microelectronics Technology and Devices -
SB Micro 2012, pp. 35-39

[37]     V. Ivanov, J. Gerber, and R. Brederlow, ‘An ultra-low power bandgap operational at supply as low as 0.75V’, Proceedings of the European Solid-State Circuits Research Conference ESSCIRC 2011, pp. 515-518

[36]     M. Lüders, B. Eversmann, J. Gerber, K. Huber, R. Kuhn, D. Schmitt-Landsiedel, and R. Brederlow‚ ‘A Fully-Integrated System Power Aware LDO for Energy Harvesting Applications’, Proceedings of the VLSI Circuits Symposium 2011, pp. 244-245

[35]     R. da Silva, G. I. Wirth, P. Srinivasan, J. Krick, and R. Brederlow, ‘Statistical Model for MOSFET Low-Frequency Noise under Cyclo-Stationary Conditions’, IEEE International Electron Device Meeting IEDM 2009 Technical Digest, pp. 715-719

[34]     G. Neuberger, F. Kastensmidt, R. Reis, G. Wirth, R. Brederlow, and Ch. Pacha, ‘Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies’, IFIP International Conference on Very Large Scale Integration 2007, pp. 78-83

[33]     M. Augustyniak, W. Weber, G. Beer, H. Mulatz, L. Elbrecht, H.-J. Timme, M. Tiebout, W. Simbürger, Ch. Paulus, B. Eversmann, D. Schmitt-Landsiedel, R. Thewes, and R. Brederlow, ‘An Integrated Gravimetric FBAR Circuit for Operation in Liquids Using a Flip-Chip Extended 0.13μm CMOS Technology’, Proceedings of the IEEE International Solid-State Circuits Conference ISSCC 2007, pp. 392-393

[32]     G. Neuberger, F. Kastensmidt, R. Reis, G. Wirth, R. Brederlow and Ch. Pacha, ‘Statistical Characterization of Hold Time Violations in 130nm CMOS Technology’, Proceedings European Solid-State Circuits Research Conference ESSCIRC 2006, pp. 114-117

[31]     M, Augustyniac, Ch, Paulus, R, Brederlow, N. Persike, G. Hartwich, D. Schmitt-Landsiedel, and R. Thewes, ‘A 24x16 CMOS-based chronocoulometric DNA mircoarray’, Proceedings of the IEEE International Solid-State Circuits Conference ISSCC 2006, pp. 46-47

[30]     R. Brederlow, R. Prakash, Ch. Paulus, and R. Thewes, ‘A low power true random number generator using random telegraph noise of single oxide-traps in small area MOSFETs’, Proceedings of the IEEE International Solid-State Circuits Conference ISSCC 2006, pp. 422-423

[29]     R. Brederlow, J. Koh, and R. Thewes, ‘A physics-based low frequency noise model for MOSFETs under periodic large signal excitation’, Proceedings of the 35th European Solid-State Device Research Conference ESSDERC 2005, pp. 333-336

[28]     R. Brederlow, J. Koh, G. I. Wirth, R. da Silva, M. Tiebout, and R. Thewes, ’Low Frequency Noise Considerations for CMOS Analog Circuit Design’ (invited), American Institute of Physics Conference Proceedings, Vol.780, 2005, pp. 703-708

[27]     R. Thewes, C. Paulus, M. Schienle, F. Hofmann, A. Frey, R. Brederlow, M. Augustyniak, M. Jenkner, B. Eversmann, P. Schindler-Bauer, M. Atzesberger, B. Holzapfl, G. Beer, T. Haneder and C.-H. Hanke, ‘CMOS-based biosensor arrays‘, Proceedings of the IEEE Design, Automation and Test in Europe DATE 2005, pp. 1222-1223

[26]     Ch. Lackner, W. Gut, T. Ostermann, R. Hagelauer, H. Klauk, M. Halik, U. Zschieschang, G. Schmid, Ch. Dehm, and R. Brederlow, ‘Demonstration of an Integrated Digital Circuit using a Pentacene Organic Transistor Technology’, Proceedings of the International Conference on Mixed Design of Integrated Circuits and Systems MIXDES 2005, pp. 87-92

[25]     H.Klauk, M. Halik, U. Zschieschang, R. Brederlow, S. Briole, M. Schütz, S. Maisch, F. Effenberger, G. Schmid, and Ch. Dehm, ‘Flexible Organic Circuits with Molecular Gate Dielectrics’, IEEE International Electron Device Meeting IEDM 2004 Technical Digest, pp. 369-372

[24]     R. Thewes, Ch. Paulus, M. Schienle, F. Hofmann, A. Frey, P. Schindler-Bauer, R. Brederlow, B. Holzapfl, M. Jenkner, B. Eversmann, M. Atzesberger, M. Augustyniak, G. Beer, M. Fritz, T. Haneder, and H.-Ch. Hanke, ’CMOS-Sensoren für Life-Sciences’ (invited), VDE-Tagung Oktober 2004, Session A3, Beitragsnr. ITG-A3.1

[23]     Ch. Pacha, M. Bach, K. von Arnim, R. Brederlow, D. Schmitt-Landsiedel, P. Seegebrecht, J. Berthold, and R. Thewes, ‘Impact of STI-Induced Stress, Inverse Narrow Width Effect, and Statistical VTH Variations on Leakage Currents in 120 nm CMOS’, Proceedings of the 34th European Solid-State Device Research Conference ESSDERC 2004,pp. 397-400

[22]     K. von Arnim, E. Borinski, P. Seegebrecht, H. Fiedler, R. Brederlow, R. Thewes, J. Berthold, and Ch. Pacha, ‘Efficiency of Body Biasing in 90 nm CMOS for Low Power Digital Circuits’, Proceedings of the 34th European Solid-State Circuits Research Conference ESSCIRC 2004, pp. 175-178

[21]     R. Thewes, Ch. Paulus, M. Schienle, F. Hofmann, A. Frey, R. Brederlow, P. Schindler-Bauer, M. Augustyniac, M. Atzesberger, B. Holzapfl, M. Jenkner, B. Eversmann, G. Beer, M. Fritz, T. Haneder, and H.-Ch. Hanke, ‘Integrated Circuits for the Biology-to-Silicon Interface’ (invited), Proceedings of the 34th European Solid-State Circuits Research Conference ESSCIRC 2004, pp. 19-28

[20]     J. Koh, R. Thewes, D. Schmitt-Landsiedel, and R. Brederlow, ‘A Circuit Design based Approach for 1/f-noise Reduction in Linear analog CMOS IC’s’, Proceedings of Very Large Scale Integrated Circuits Symposium VLSI 2004, pp. 222-225

[19]     S. Briole, Ch. Pacha, K. Goser, A. Kaiser, R. Thewes, W. Weber, and R. Brederlow, ‘Towards the one-cent RF ID tag: Low cost ac-only driven circuits and side-wall contact packaging’, Proceedings of the IEEE International Solid-State Circuits Conference ISSCC 2004, pp. 438-439

[18]     R. Brederlow, S. Zauner, A. L. Scholtz, K. Aufinger, W. Simbürger, C. Paulus, A. Martin, M. Fritz, H.-J. Timme, H. Heiss, S. Marksteiner, L. Elbrecht, R. Aigner, and R. Thewes, ‘Bio-chemical sensors based on bulk acoustic wave resonators’, IEEE International Electron Device Meeting 2003 Technical Digest, pp. 992-994

[17]     H. Klauk, M. Halik, U. Zschieschang, G. Schmid, Ch. Dehm, R. Brederlow, S. Briole, M. Schütz, S. Maisch, and F. Effenberger, ‘Molecular TFTs with a sub-threshold swing of 100mV/decade’, IEEE International Electron Device Meeting IEDM 2003 Technical Digest, pp. 195-199

[16]     Ch. Schlünder, R. Brederlow, B. Ankele, A. Lill, K. Goser, and R. Thewes, ‘On the Degradation of P-MOSFETs in Analog and RF Circuits under Inhomogeneous Negative Bias Temperature Stress‘, Proceedings of the 41th IEEE International Reliability Physics Symposium IRPS 2003, pp. 5-10

[15]     B. Eversmann, M. Jenkner, Ch. Paulus, R. Brederlow, F. Hofmann, B. Holzapfl, R. Thewes, P. Fromherz, R. Gabl, G. Eckstein, and D. Schmitt-Landsiedel, ‘A 128 x 128 CMOS Sensor Array for Monitoring Neural Signals of Living Cells’, Proceedings of the IEEE International Solid-State Circuits Conference 2003, pp. 222-223

[14]     R. Brederlow, S. Briole, H. Klauk, M. Halik, U. Zschieschang, G. Schmid, J.-M. Gorriz-Saez, Ch. Pacha, R. Thewes, and W. Weber, ‘Evaluation of the performance potential of organic TFT circuits on flexible substrates‘, Proceedings of the IEEE  International Solid-State Circuits Conference ISSCC 2003, pp. 378-379

[13]     H. Klauk, M. Halik, U. Zschieschang, G. Schmid, W. Radlik, R. Brederlow, S. Briole, Ch. Pacha, R. Thewes, and W. Weber, ‘Polymer Gate Dielectric Pentacene TFTs and Circuits on Flexible Substrates’, IEEE International Electron Device Meeting IEDM 2002 Technical Digest, pp. 557-560

[12]     R. Brederlow, G. Wenig, and R. Thewes, ‘Investigation of the Thermal Noise of MOS Transistors under Analog and RF Operating Conditions’, Proceedings of the 32th European Solid-State Device Research Conference ESSDERC 2002, pp. 87-90

[11]     R. Thewes, R. Brederlow, Ch. Schlünder, P. Wieczorek, B. Ankele, A. Hesener, J. Holz, S. Kessel, and W. Weber, ‘Evaluation of MOS Reliability in Analog Applications’ (invited), Proceedings of the 31th European Solid-State Device Research Conference ESSDERC 2001, pp. 73-80

[10]     Ch. Paulus, R. Brederlow, U. Kleine, and R. Thewes, ‘An Efficient and Precise Design Method to Optimize Device Areas in Mismatch and Flicker-Noise Sensitive Analog Circuits‘, Proceedings of the IEEE International Conference on Electronics Circuits and Systems  ICESS 2001, pp. 107-111

[9]       R. Thewes, C. Linnenbank, U. Kollmer, S. Burges, M. Di Leo, M. Clinchy, U. Schaper, R. Brederlow, R. Seibert, and W. Weber, ‘On the Matching Behavior of MOSFET Small Signal Parameters’, Proceedings of the International Conference on Microelectronic Test Structures ICMTS 2000,
pp. 137-141

[8]       R. Thewes, R. Brederlow, Ch. Schlünder, P. Wieczorek, A. Hesener, B. Ankele, P. Klein, S. Kessel, and W. Weber, ‘Device Reliability in Analog CMOS Applications’ (invited), IEEE International Electron Device Meeting IEDM 1999 Technical Digest, pp. 81-84

[7]       R. Brederlow, W. Weber, D. Schmitt-Landsiedel, and R. Thewes 'Fluctuations in the Low Frequency Noise of MOS-Transistors and their Modeling in analog and RF-Circuits', IEEE International Electron Device Meeting IEDM 1999 Technical Digest, pp. 159-162

[6]       R. Thewes , G. H. Walter, R. Brederlow, Ch. Schlünder, A. v. Schwerin, R. Jurk, C. Linnenbank, G. Legauer, D. Schmitt-Landsiedel, and W. Weber, ‘Channel Length Dependence of Hot Carrier Degradation of LATID-n-MOSFETs under Analog Operation’, Proceedings of the 37th IEEE International Reliability Physics Symposium IRPS 1999, pp. 233-238

[5]       R. Brederlow, W. Weber, D. Schmitt-Landsiedel, and R. Thewes, 'Investigation of the Hot Carrier Degradation of Low Frequency Noise Behavior of MOS Transistors under Analog Operation', Proceedings of the 37th IEEE International Reliability Physics Symposium IRPS 1999, pp. 239-242

[4]       R. Thewes, R. Brederlow, C. Dahl, U. Kollmer, C. Linnenbank, B. Holzapfel, J. Becker, J. Kissing, S. Kessel, and W. Weber, 'Explanation and Quantitative Model for the Matching Behavior of Poly-Silicon Resistors', IEEE International Electron Device Meeting IEDM Technical Digest, 1998, pp. 771-774

[3]       R. Brederlow, W. Weber, C. Dahl, D. Schmitt-Landsiedel, and R. Thewes, 'A Physically Based Model for Low-Frequency Noise of Poly-Silicon Resistors', IEEE International Electron Device Meeting 1998 Technical Digest, pp. 89-93

[2]       C. Linnenbank, W. Weber, U. Kollmer, B. Holzapfel, S. Sauter, U. Schaper, R. Brederlow, S. Cyrusian, S. Kessel, R. Heinrich, E. Hoefig, G. Knoblinger, A. Hesener, and R. Thewes, 'What Do Matching Results of Medium Area MOSFETs Reveal for Large Area Devices in Typical Analogue Applications?', Proceedings of the 28th European Solid State Device Research Conference ESSDERC 1998, pp. 104-107

[1]          R. Brederlow, W. Weber, R. Jurk, C. Dahl, S. Kessel, J. Holz, W. Sauert, P. Klein, B. Lemaitre, D. Schmitt-Landsiedel, and R. Thewes, ‘Influence of Fluorinated Gate Oxides on the Low Frequency Noise of MOS Transistors under Analog Operation', Proceedings of the 28th European Solid State Device Research Conference ESSDERC 1998, pp. 472-475