Module Number: EI5042
Duration: 1 Semeseter
Occurence: Winter/summer semester
Number of ECTS: 6
Professor in charge: Andreas Herkersdorf
Contact hours: 60
Self-studying hours: 120
Examination with the following elements:
- 30 minute oral presentation of design per student group (30%)
- 5 page written deliverable (documentation) per student (50%)
- inspection of implemented system (20%)
Exam type: oral
Exam duration: 30 min.
Possibility of re-taking: In the next semester: Yes; at the end of the semester: No
Written paper: No
Prerequisite is a completed VHDL course, e.g.
- HDL Design Lab (EDA Institute) or
- Praktikum VHDL (LIS, for German students) or
- VHDL course form home university (BSc program)
A VLSI architecture is designed by a group of students:
System design (architecture and partitioning), hardware specification and verification (functionality and interfaces), simulation and synthesis, implementation in FPGA; project management: coordination integration of submodules, verification in system enviroment
At the end of the module students are able to understand HW system specifications and HW design flows from system specification to system test. They are able to implement an IC design with VHDL, they gain experience in teamwork (self-organized taks distribution and coordination) as well as presentation of their work results.
- Learning method: In addition to the individual methods of the students consolidated knowledge is aspired by introductory lessons
- Teaching method: During the lectures students are instructed in a teacher-centered style. The lab is performed by the students' self-coordination assisted by a student tutor.
The following kinds of media are used:
- Lab Task Description (35 page booklet) / 3 x 90 minute lab introduction (lecture style)
The following literature is recommended:
- Z. Navabi, VHDL - Analysis and Modelling of Digital Systems, McGraw Hill
- P. Ashenden, The VHDL Cookbook