Module Number: EI50141
Duration: 1 Semester
Occurence: Winter Semester
Number of ECTS: 5
Professor in charge: Jan Otterstedt
Contact hours: 45
Self-study hours: 105
Exam type: oral
Exam duration (min.): 30
Possibility of retaking: In the next semester: Yes; at the end of the semester: No
Written paper: No
Basics of digital circuit designThe following modules should be passed before taking the course:
- Digital IC-Design
- Electronic Design Automation
Principles of testing digital circuits; fault models and test quality; functional and structural test generation; fault simulation; complexity theory; design for test (passive, active test methods); memory test; test standards; miscellaneous topics (Iddq test, analog test, test pattern compression, yield management);In detail:The manufacturing process of integrated circuits introduces a large variety of physical defects. In order to prevent the delivery of failing silicon devices to the customer, the correct function of delivered integrated circuits has to be guaranteed by testing all devices after they have been fabricated.Testing integrated circuits is one of the core competencies of a semiconductor company. It represents a significant factor in costs and quality. Therefore, testing is considered as an outstanding part of the entire design and manufacturing process of ICs.Furthermore, testing is a domain-crossing topic: The test engineer within a semiconductor company requires a broad expertise covering circuit and system design, circuit simulation and design verification, and physical design.One of the main challenges in testing is costs which have drastically increased over the past years. The access to circuit internal transistors and nodes has to be accomplished by a limited number of external pins. This is increasingly difficult due to the continuous shrinking of device structures.
This lecture conveys:
- The basic idea of testing.
- Relevant failure mechanisms of integrated circuits and the common fault models.
- The complexity problem of testing and its resulting limitations.
- Methods for test pattern generation (e.g. fault simulation and automatic test generation).
- Fundamental measures for designing integrated circuits in order to raise their testability (Design-for-Testability).
- Techniques for insertion of built-in self-test (BIST) in integrated circuits.
- Techniques for memory testing.
At the end of the module students know about the following topics and are able to employ this knowledge to define and evaluate test solutions for digital ICs and systems:
Definition of testing and the difference to verification
Fundamentals of testing: fault models, fault detection, redundant faults, fault coverage
Methods for test generation: Boolean differences, D-algorithm, fault simulation- Analysis of test complexity with the help of complexity theory
Principles of passive test methods: Ad-hoc measures, scan path / Principles of active test methods: BIST- Overview over memory fault models and memory test algorithms.
Outline of test standards (IEEE boundary scan test) and additional topics like IDDQ testing, analog testing, fault analysis
- Learning method: In addition to the individual methods of the students consolidated knowledge is aspired by repeated lessons in exercises and tutorials.
- Teaching method: During the lectures students are instructed in a teacher-centered style. The exercises are held in a student-centered way. Where applicable, each of the 10 chapters of the lectures is immediately followed by an associated exercise/tutorial block.
The following kinds of media are used:
- Handouts of the presentations and additional lecture notes
- Handouts of exercises
The following literature is recommended:
- Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits; M. Bushnell, V. Agrawal; Kluwer Academic Publishers, 2000.
- Digital Systems Testing and Testable Design; M. Abramovici, M. Breuer, A. Friedmann; Computer Science Press, 1990