Grundlagen der IT-Sicherheit: Screencasts der Hausaufgaben
Beschreibung
Für das WS20/21 werden für das Modul "Grundlagen der IT-Sicherheit" Screencasts für mögliche Lösungen der Hausaufgaben aufgenommen. Hierfür suchen wir ab April 2020 eine/einen Back-End Werkstudent/in, der/die unter anderem bei den folgenden Aufgaben unterstützt:
Equipment Setup und Test
Erstellung des Drehbuchs
Recherche von weiterführenden Themen
Screencast Editing
Die Themen der Hausaufgaben sind unter anderem:
Password Cracking
Zertifikate
SQL Injection
Access Control
WPA2 Hacking
Hardware Security
Datenschutz und Tracking
Voraussetzungen
Ein Hintergrund in IT-Sicherheit ist zwar hilfreich, aber nicht unbedingt notwendig.
Kontakt
Johanna Baehr Technische Universität München Fakultät für Elektrotechnik und Informationstechnik Lehrstuhl für Sicherheit in der Informationstechnik
Raum N1014 80333 München
Tel.: +49 89 289 28246 johanna.baehr@tum.de
Betreuer:
Johanna Baehr
Working Student - Hardware Reverse Engineering Tools
Working Student - Hardware Reverse Engineering Tools
Beschreibung
We are currently looking for a working student to test, maintain and document existing python tools for hardware reverse engineering. Furthermore, we are also looking to implementation and maintain a new database setup. Interested students should be proficient in python.
Voraussetzungen
Python
SQL
Verilog
Kontakt
Johanna Baehr Technische Universität München Fakultät für Elektrotechnik und Informationstechnik Lehrstuhl für Sicherheit in der Informationstechnik
Raum N1014 80333 München
Tel.: +49 89 289 28246 johanna.baehr@tum.de
Betreuer:
Johanna Baehr
Current Student Work
Bachelorarbeiten
Analysis of the Effect of Netlist Errors on Machine Learning based Hardware Reverse Engineering
Analysis of the Effect of Netlist Errors on Machine Learning based Hardware Reverse Engineering
Beschreibung
The final step of hardware reverse engineering is the identification of the functionality of a chip, after it has been delayered and imaged. This is often done by matching against known designs. Machine Learning methods can be applied to improve the identification. In this work, the applicability of pattern matching, classification alogrithms or Neural Nets should be tested and analysed.
Voraussetzungen
python / C
Kontakt
Johanna Baehr
Chair for Security in Information Technology Head: Prof. Dr.-Ing. Georg Sigl Technical University of Munich Arcisstr. 21, 80333 Munich (Germany)
The final step of hardware reverse engineering is the identification of the functionality of a chip, after it has been delayered and imaged. This is often done by matching against known designs. Machine Learning methods can be applied to improve the identification. In this work, the applicability of pattern matching, classification alogrithms or Neural Nets should be tested and analysed.
Betreuer:
Johanna Baehr
Machine Learning for Reverse Engineering - Design Flow
Machine Learning for Reverse Engineering - Design Flow
Beschreibung
The final step of hardware reverse engineering is the identification of the functionality of a chip, after it has been delayered and imaged. This is often done by matching against known designs. Machine Learning methods can be applied to improve the identification. In this work, the applicability of pattern matching, classification alogrithms or Neural Nets should be tested and analysed.
Betreuer:
Johanna Baehr
Breaking Obfuscation: Machine Learning for Circuit Recognition by Structural Analysis
Breaking Obfuscation: Machine Learning for Circuit Recognition by Structural Analysis
Beschreibung
The final step of hardware reverse engineering is the identification of the functionality of a chip, after it has been delayered and imaged. This is often done by matching against known designs. Machine Learning methods can be applied to improve the identification. In this work, the applicability of pattern matching, classification alogrithms or Neural Nets should be tested and analysed.
Stichworte: Hardware Reverse Engineering, Netlist Modeling, Synthesis and Layout
Beschreibung
In a realistic Reverse Engineering Scenario, where a chip is delayered, imaged and then analysed, errors during earlier steps will hinder the later analysis. In order to better understand the effect of these errors on the steps for reverse engineering, this work should model errors which can occur during reverse engineering, and analyse their effect.
Voraussetzungen
Idealy:
Python / C
VHDL / Verilog
Kontakt
Johanna Baehr
Chair for Security in Information Technology Head: Prof. Dr.-Ing. Georg Sigl Technical University of Munich Arcisstr. 21, 80333 Munich (Germany)
Logic locking has become one of the more promising methods to protect hardware designs against IP Infringement and Hardware Attacks - for example through the insertion of Hardware Trojans. This work should look into existing tools which automate the locking process, as well as automating known methods which are not yet included in existing tools.
Voraussetzungen
Idealy:
Python / C
Verilog / VHDL
Kontakt
Johanna Baehr
Chair for Security in Information Technology Head: Prof. Dr.-Ing. Georg Sigl Technical University of Munich Arcisstr. 21, 80333 Munich (Germany)
The final step of hardware reverse engineering is the identification of the functionality of a chip, after it has been delayered and imaged. This is often done by matching against known designs. Machine Learning methods can be applied to improve the identification. In this work, the applicability of pattern matching, classification alogrithms or Neural Nets should be tested and analysed.
Voraussetzungen
python / C
Kontakt
Johanna Baehr
Chair for Security in Information Technology Head: Prof. Dr.-Ing. Georg Sigl Technical University of Munich Arcisstr. 21, 80333 Munich (Germany)
Baehr, Johanna; Bernardini, Alessandro; Sigl, Georg; Schlichtmann, Ulf: Machine Learning and Structural Characteristics for Reverse Engineering. 24th Asia and South Pacific Design Automation Conference Conference (ASPDAC’19), 2019Tokyo, Japanmehr…BibTeX
Brunner, M. and Baehr, J. and Sigl, G.: Improving on State Register Identification in Sequential Hardware Reverse Engineering. 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2019Washington, D.C., USAmehr…BibTeX
2018
Werner, M.; Lippmann, B.; Baehr, J.; Gräb, H.: Reverse Engineering of Cryptographic Cores by Structural Interpretation Through Graph Analysis. 2018 IEEE 3rd International Verification and Security Workshop (IVSW), 2018Platja d’Aro, Costa Brava, Spain, 13-18 mehr…BibTeX
