If you are interested to be involved in one of my research topics as part of your Bachelor Thesis, Master Thesis or research internship, feel free to contact me. In addition to the topics below, also unsolicited applications are always welcome.
Hardware obfuscation gains more and more attention in the area of IP protection. It is used to prevent IP overproduction, IP theft or counterfeiting. A special case of hardware obfuscation on gate-level netlists is sequential obfuscation which targets memory elements in a circuit [1] or the finite state machine structure [2].
The aim of this work is to improve and enhance sequential hardware obfuscation.
Please contact me to get more information about the topic and the aim of this work.
Reference:
[1] Karmakar, Rajit, Santanu Chatopadhyay, and Rohit Kapur. "Encrypt flip-flop: A novel logic encryption technique for sequential circuits." arXiv preprint arXiv:1801.04961 (2018).
[2] Chakraborty, Rajat Subhra, and Swarup Bhunia. "HARPOON: An obfuscation-based SoC design methodology for hardware protection." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28.10 (2009): 1493-1502.
Voraussetzungen
Basic knowledge in Python
Basic knowledge in Verilog or VHDL
Kontakt
Michaela Brunner, M.Sc.
Technical University of Munich, Chair of Security in Information Technology
The aim of sequential netlist reverse engineering is to extract the control logic out of a given design netlist. In order to derive this information, first, the existing flip-flops have to be classified into state flip-flops which belong to the control logic and data flip-flops. Based on the correctly classified state flip-flops the control logic can be extracted in form of a finite state machine. There exist already a number of different state flip-flop identification methods which use various strategies for classification [1] [2].
The aim of this work is to improve and enhance flip-flop classification.
Please contact me to get more information about the topic and the aim of this work.
Reference:
[1] Brunner, Michaela, Johanna Baehr, and Georg Sigl. "Improving on state register identification in sequential hardware reverse engineering." 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2019.
[2] Fyrbiak, Marc, et al. "On the difficulty of fsm-based hardware obfuscation." IACR Transactions on Cryptographic Hardware and Embedded Systems (2018): 293-330.
Voraussetzungen
Basic knowledge in Python
Basic knowledge in Verilog or VHDL
Basic knowledge in simulating designs
Kontakt
Michaela Brunner, M.Sc.
Technical University of Munich, Chair of Security in Information Technology
Hardware obfuscation gains more and more attention in the area of IP protection. It is used to prevent IP overproduction, IP theft or counterfeiting. A special case of hardware obfuscation on gate-level netlists is sequential obfuscation which targets memory elements in a circuit [1] or the finite state machine structure [2].
The aim of this work is to improve and enhance sequential hardware obfuscation.
Please contact me to get more information about the topic and the aim of this work.
Reference:
[1] Karmakar, Rajit, Santanu Chatopadhyay, and Rohit Kapur. "Encrypt flip-flop: A novel logic encryption technique for sequential circuits." arXiv preprint arXiv:1801.04961 (2018).
[2] Chakraborty, Rajat Subhra, and Swarup Bhunia. "HARPOON: An obfuscation-based SoC design methodology for hardware protection." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28.10 (2009): 1493-1502.
Voraussetzungen
Basic knowledge in Python
Basic knowledge in Verilog or VHDL
Kontakt
Michaela Brunner, M.Sc.
Technical University of Munich, Chair of Security in Information Technology
The aim of sequential netlist reverse engineering is to extract the control logic out of a given design netlist. In order to derive this information, first, the existing flip-flops have to be classified into state flip-flops which belong to the control logic and data flip-flops. Based on the correctly classified state flip-flops the control logic can be extracted in form of a finite state machine. There exist already a number of different state flip-flop identification methods which use various strategies for classification [1] [2].
The aim of this work is to improve and enhance flip-flop classification.
Please contact me to get more information about the topic and the aim of this work.
Reference:
[1] Brunner, Michaela, Johanna Baehr, and Georg Sigl. "Improving on state register identification in sequential hardware reverse engineering." 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2019.
[2] Fyrbiak, Marc, et al. "On the difficulty of fsm-based hardware obfuscation." IACR Transactions on Cryptographic Hardware and Embedded Systems (2018): 293-330.
Voraussetzungen
Basic knowledge in Python
Basic knowledge in Verilog or VHDL
Basic knowledge in simulating designs
Kontakt
Michaela Brunner, M.Sc.
Technical University of Munich, Chair of Security in Information Technology
Brunner, M. and Gruber, M. and Tempelmeier, M. and Sigl, G.: Logic Locking Induced Fault Attacks. 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020Limassol, CYPRUSmehr…BibTeX
Zhang, G. L. and Li, B. and Li, M. and Yu, B. and Pan, D. Z. and Brunner, M. and Sigl, G. and Schlichtmann, U.: TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing. IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systemsde
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, 2020, 1-1 mehr…BibTeX
Zhang, G. L. and Brunner, M. and Li, B. and Sigl, G.and Schlichtmann, U.: Timing Resilience for Efficient and Secure Circuits. 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 2020Beijing, China, 623-628 mehr…BibTeX
2019
Brunner, M. and Baehr, J. and Sigl, G.: Improving on State Register Identification in Sequential Hardware Reverse Engineering. 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2019Washington, D.C., USAmehr…BibTeX
